Patents Assigned to Fujitsu VLSI Limited
  • Patent number: 5334846
    Abstract: A charged particle beam exposure apparatus is provided with a source for irradiating a charged particle beam on an object which has a position detection mark provided thereon and is carried on a movable stage, a deflection part for deflecting the charged particle beam based on deflection signals, a first detection part for detecting the position detection mark of the object, a second detection part for detecting a stage position of the object and for outputting a position detection signal, a moving part for moving the stage which carries the object, and a control unit for controlling inputs and outputs of the source, the deflection part, the first and second detection parts and the moving part.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: August 2, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Mitsuhiro Nakano, Junichi Kai
  • Patent number: 5327387
    Abstract: A dynamic random access memory comprises a CBR refresh detection unit for detecting a commencement of a CBR refreshing cycle and a control signal generation unit for deactivating data output during the CBR cycle, both of the CBR refresh detection unit and the control signal generation unit being supplied with a /RAS signal and a /CAS signal simultaneously, wherein the dynamic random access memory further comprises a CBR refresh control unit supplied with an output of the CBR refresh detection unit and further with an output of the control signal generation unit for producing a control signal during the CBR refreshing cycle such that the control signal is produced in response to the leading edge of the /RAS signal and terminated in response to the trailing edge of the /CAS signal.
    Type: Grant
    Filed: November 5, 1992
    Date of Patent: July 5, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Akira Sugiura, Yukinori Kodama
  • Patent number: 5319607
    Abstract: The present invention relates to a semiconductor unit including a delay circuit used for an address transition detecting circuit in a storage, wherein a change of an address is detected and, accordingly, an access address in a memory cell is altered. The present invention aims at ensuring extending an address signal even though that of a short pulse width is provided, and at outputting an address transition detection signal of a predetermined pulse width, thereby stabilizing the operation of the circuit and improving its reliability. The present invention includes a second address extending circuit having a complementary transistor circuit, a capacitor connected to the output part of the complementary transistor circuit, and a resistor serially connected between a pair of complementary transistors.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: June 7, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Yasuhiro Fujii, Hirohiko Mochizuki, Yukinori Kodama, Akira Sugiura
  • Patent number: 5314724
    Abstract: A process for the formation of a silicon oxide film, comprising the steps of exciting a gas comprising an organosilane or organosiloxane gas and a gas containing H and OH above a substrate in a reaction chamber to react them with each other in a gaseous phase or on the substrate, thereby depositing a thin film of an organic-group-containing silanol, silanol polymer, or siloxane-bonded polymer on the substrate, and removing the organic groups from the thin film to form a silicon oxide film. Preferably, the formation of a film is conducted while repeating the step of deposition and the step of removing the organic groups through a plasma treatment within an identical chamber, and the film is further heat-treated at a temperature of C. or below. Thus, a good insulating film having a flatness comparable to that of an SOG film can be obtained.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: May 24, 1994
    Assignees: Fujitsu Limited, Fujitsu VlSI Limited
    Inventors: Atuhiro Tsukune, Yuji Furumura, Hatanaka Masanobu
  • Patent number: 5309040
    Abstract: In a semiconductor integrated circuit for taking in an external power source voltage from outside the semiconductor chip, the external power source voltage is dropped by a voltage dropping unit installed inside the semiconductor chip and the external power source voltage in the semiconductor integrated circuit, as dropped is supplied as an internal power source voltage to the semiconductor chip and used as the internal power source voltage, a plurality of voltage dropping units are installed for each of a plurality of semiconductor circuit block installed inside the semiconductor chip, and the voltage fluctuation of an internal power source is effectively suppressed in the event that a circuit consuming a very high current is operated.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: May 3, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Tomio Nakano, Yoshiharu Kato, Hidenori Nomura
  • Patent number: 5304923
    Abstract: An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.
    Type: Grant
    Filed: September 14, 1992
    Date of Patent: April 19, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Masahiro Tanaka, Kazuhiro Tomita, Kazumi Ogawa
  • Patent number: 5302951
    Abstract: In an digital/analog converter having a conversion circuit for converting a digital signal into an analog signal, and an output voltage follower connected to the conversion circuit, a voltage amplitude lowering circuit for lowering an amplitude of power supply voltages applied to the conversion circuit to conform to an amplitude of a linear output of the voltage follower, and a voltage amplitude enlarging circuit for enlarging the amplitude of the output of the voltage follower.
    Type: Grant
    Filed: February 11, 1993
    Date of Patent: April 12, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Masahiro Yamashita
  • Patent number: 5297080
    Abstract: A sense amplifier in a semiconductor memory device includes a detection unit for generating complementary state signals showing a state of a pair of bit lines coupled to a plurality of memory cells in the semiconductor memory device in which word lines are coupled to the memory cells, and a latch circuit for receiving the complementary signals and a reference signal and for inverting states of complementary output signals of the latch means only when one of the complementary state signals decreases and becomes lower than the reference voltage.
    Type: Grant
    Filed: July 9, 1991
    Date of Patent: March 22, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Yasuhiro Yamamoto
  • Patent number: 5287019
    Abstract: A level conversion circuit includes an ECL logic circuit including a current switch circuit having first and second transistors, each of the transistors having an emitter coupled to each other and at least one thereof receiving an input signal of ECL logic level, and an output transistor coupled to a collector of at least one of the first and second transistors; a current control circuit including a current mirror circuit having third and fourth transistors, at least one of the transistors being coupled to an output end of the output transistor, and controlling a current flowing through the output to thereby carry out a level conversion of a signal at the output end; and a switch circuit operative coupled to the current control circuit. The switch circuit responds to a control signal and thus controls a supply of a current or a break thereof from the output transistor to the current control circuit.
    Type: Grant
    Filed: November 6, 1991
    Date of Patent: February 15, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Kazuyuki Nonaka, Shinji Saito, Tetsuya Aisaka, Takehiro Akiyama, Kouzi Takekawa
  • Patent number: 5283872
    Abstract: In a SCSI device in a small computer system including a plurality of apparatuses, each apparatuses having a SCSI device connected to the apparatus by a MPU bus, and connected to each other through the SCSI device and a SCSI bus.
    Type: Grant
    Filed: March 13, 1991
    Date of Patent: February 1, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Masatoshi Ohnishi
  • Patent number: 5281873
    Abstract: A sense amplifier control circuit controls the activation and deactivation of sense amplifiers without a lowering of the operation speed of the sense amplifiers, correctly carries out a control operation without malfunctions, and is suitable for highly integrated circuits. The control circuit comprises a control unit, and each of the sense amplifiers comprises a pair of transistors forming a differential pair and a constant current source transistor connected to a common node of the differential pair. The control unit is connected to the constant current source transistors and generates a constant current source control signal in response to control signal indicating an activation or deactivation of the differential amplification operation of each differential pair.
    Type: Grant
    Filed: May 17, 1993
    Date of Patent: January 25, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Teruo Seki
  • Patent number: 5278788
    Abstract: In a semiconductor memory device wherein a difference in potential of two data buses is increased during a write mode and is reduced during a read mode, a write/restoring circuit is provided for carrying out a write operation which increases the difference in potential between the data buses and a restoring operation which reduces the increased difference in potential of the data buses to carry out a read operation after the write operation in accordance with a common write control signal using common output transistors.
    Type: Grant
    Filed: March 7, 1991
    Date of Patent: January 11, 1994
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Hidenori Nomura
  • Patent number: 5262682
    Abstract: A level converter circuit having hysteresis characteristics between an input voltage and an output voltage comprises two multi-collector transistors constituting a differential amplifier, a reference voltage control unit for controlling a reference voltage supplied to the differential amplifier, and an output level switching unit for switching and outputting the output voltage between a first voltage level and a second voltage level. The reference voltage control unit is connected to first collectors of the two multi-collector transistors, and the output level switching unit is connected to second collectors of the two multi-collector transistors. Therefore, an occupied area of the level converter circuit can be small and a circuit configuration can be simplified, and thus the level converter circuit can be applied to a masterslice type LSI. Further, a chip area including the level converter circuit can be small and cost thereof can be reduced.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: November 16, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Yoshimasa Mitsuya, Katsuya Shimizu
  • Patent number: 5260705
    Abstract: An analog-to-digital (A/D) converter has a simple arrangement and achieves an accurate high-speed A/D converting operation. The A/D converter comprises an analog data input unit (2), an A/D conversion circuit (3), a controller (4) for controlling the A/D conversion circuit (3), and a digital data output unit (100). The controller (4) includes a sampling time controller (5) and a bit conversion time controller (6).
    Type: Grant
    Filed: March 19, 1992
    Date of Patent: November 9, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventor: Keizo Inukai
  • Patent number: 5248909
    Abstract: A level converting circuit converts a first signal which has an ECL level which is used in an ECL device into a second signal which has a GaAs logic level which is used in a GaAs device which is based on a GaAs substrate.
    Type: Grant
    Filed: July 29, 1992
    Date of Patent: September 28, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Kouju Aoki, Hideji Sumi, Moriaki Mizuno, Tetsuya Aisaka
  • Patent number: 5245524
    Abstract: A DC-DC converter includes first and second capacitors coupled in parallel, a switching part for controlling the first and second capacitors so that the first capacitor is charged by an input voltage and the second capacitor is charged by a discharging of the first capacitor, an output voltage being obtained at one end of the second capacitor, and the switching part including a discharge path through which the second capacitor is discharged. An output voltage detection units detects the output voltage and determines whether or not the output voltage satisfies a predetermined condition. A discharge path breaking units breakes the discharge path when the output voltage detection unit determines that the output voltage satisfies the predetermined condition, so that the first capacitor is prevented from being discharged through discharge path.
    Type: Grant
    Filed: October 31, 1991
    Date of Patent: September 14, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Shinichi Nakagawa, Hidenobu Ito
  • Patent number: 5239508
    Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus.
    Type: Grant
    Filed: July 16, 1991
    Date of Patent: August 24, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Hidenori Nomura, Yoshiharu Kato, Eisaku Itoh
  • Patent number: 5222226
    Abstract: A microprocessor has a memory part including a memory for storing programs, a central processing unit for carrying out an operation on a data stored in the memory part depending on the programs stored in the memory, a holding part for entering an address region information with a predetermined timing and for holding the address region information, which indicates an allocation of a predetermined address region for the memory, an address generating part for generating an address of a command which is to be executed next, and an access enable part for enabling access to the memory when the address generated by the address generating part is included in the predetermined address region.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: June 22, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Satoru Yamaguchi, Hitoshi Takahashi
  • Patent number: 5222041
    Abstract: A data amplifying system in a semiconductor memory includes a current mirror circuit for receiving, via a data bus, an input signal corresponding to data read out from a memory cell via a pair of bit lines and for amplifying the input signal. The current mirror circuit operates on the basis of a power supply voltage. An amplitude limit circuit receives an operation voltage and limits the amplitude of the input signal on the data bus to a predetermined potential range on the basis of the operation voltage. A bit line reset potential generator generates a bit line reset potential and applies the bit line reset potential to the bit lines and the amplitude limit circuit. The bit line reset voltage is lower than the power supply line and serves as the operation voltage applied to the amplitude limit circuit.
    Type: Grant
    Filed: July 25, 1991
    Date of Patent: June 22, 1993
    Assignee: Fujitsu VLSI Limited
    Inventors: Miki Nishimori, Hidenori Nomura
  • Patent number: 5218238
    Abstract: A bias voltage generation circuit comprises a bias voltage generation portion having a bias control node, a first switching unit, and a second switching unit. The bias voltage generation portion is used to generate a bias voltage of a predetermined potential and supply the bias voltage to an ECL circuit during an operation period, and the first switching unit is used to drop the bias voltage during a standby period in response to a bias voltage control signal. The second switching unit is used to switch OFF during the standby period to cut off a current flow through the bias control node and switch ON during the operation period to supply a current through the bias control node in response to the bias voltage control signal. Consequently, a current flow during the standby period can be reduced, and power consumption of the bias voltage generation circuit during the standby period is minimal.
    Type: Grant
    Filed: March 13, 1992
    Date of Patent: June 8, 1993
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Kazuyuki Nonaka, Tetsuya Aisaka