Abstract: An arithmetic logic unit (ALU) is disclosed, which is capable of shortening the zero-detection time. The ALU comprises a combinational circuit, a first and second zero detectors and a selector. The arithmetic device performs a mathematical operation on a first and second binary numbers to produce an operational result. The first zero detector determines whether the operational result of the arithmetic device is zero, based on the first and second binary numbers directly input to the first zero detector, concurrent with mathematical operation being executed by the combinational circuit. The second zero detector determines whether the operation result of the combinational circuit is zero, based on the operational result supplied thereto. The selector selects a detection output of one of the first and second zero detectors, based on a control signal supplied thereto.
Abstract: A method for ashing a resist on a wafer in a plasma reaction chamber comprises the steps of flowing a non-activated oxygen containing gas into the plasma reaction chamber immediately before loading the wafer to the plasma reaction chamber, and then carrying out a plasma ashing of the resist. In one of the preferred embodiments, after the reaction chamber was exposed to the atmosphere and then evacuated to vacuum, a mixed gas of oxygen (90% in volume) and water vapor (10% in volume) was flown into the reaction chamber with 1000 seem and 1 Torr for 5 min. and subsequently the ashing was carried out. The method prevents the ashing rate from decreasing with ashing time.
Abstract: In a semiconductor memory device with redundant configuration, a redundant address detection circuit is additionally provided between an I/O buffer and a read/write circuit coupled to a memory cell array. The detection circuit receives both a signal indicating the detection of redundancy from a redundant address setter and a signal instructing a test mode for the memory device, and selectively inverts the logic of data associated with the redundant cell. When the data is supplied to memory cells through the redundant address detection circuit under test mode conditions, only data involved in a redundant address is inverted in logic and is written into a redundant cell. Subsequently, a tester reads out the write data of all memory cells to produce a bit map indicating the address of the inverted data and allowing the tester to detect the address of redundant memory cells.
Abstract: A data access controller for a disc device is disclosed for accessing data on a disc. A control unit, controlling the disc device, outputs a mode switching signal. A mark detector detects the sector mark and the address mark in read data from a target sector, and outputs a first and second detection signals indicative of the detections of the sector mark and address mark, respectively. In response to the mode switching signal, the mark detector enters a first search mode to detect all data bits of the target sector. A physical address read circuit reads physical address data in the read data in response to the second detection signal, and outputs a synchronizing signal. The format counter receives a basic clock signal to count the number of pulses of the clock signal, and resets its count value to a prescribed value in accordance with the first detection signal and the synchronizing signal to synchronize its count value with the position of the drive head on the target sector.
Abstract: A semiconductor memory device executes the control of data input/output in accordance with control signals and address signals. The device includes data buses, a memory cell array including a plurality of memory cells, a circuit for selecting a specific memory cell from the memory cells to provide the data buses with cell information data stored in the selected cell and data output control circuit for controlling data output from the memory device, based on at least one control signal provided to the control circuit. The control circuit has an output terminal for outputting the output data, and maintains the terminal at a high-impedance state as long as the cell information provided on the data buses is not supplied to the control circuit.
Abstract: A semiconductor memory device writes data to memory cells contained in the memory device in response to an enable signal supplied thereto. The memory device includes, a pair of bit lines connected to the memory cells, and a sense amplifier connected to the pair of bit lines to latch cell data read from the memory cells. The pair of bit lines couples to a data writing circuit, which writes data to the memory cells in response to the first enable signal. The memory device also includes a switching circuit connected to the sense amplifier, for disabling the sense amplifier in response to the first enable signal.
Abstract: An oscillation circuit is disclosed, which comprises an input stage, intermediate stage and output stage circuits which are coupled to one another. The input stage circuit is composed of a hysteresis inverter having a first threshold value and a second threshold value that is set between the first threshold value and the potential of a first power supply. The intermediate stage circuit includes an inversion circuit and a delay circuit that is provided between the hysteresis inverter and the inversion circuit. The output stage circuit includes an output terminal connected to the hysteresis inverter, a capacitor provided between the output terminal and the first power supply and an inverter circuit connected to the inversion circuit. The inverter circuit controls the charging and discharging of the capacitor to generate an oscillation output signal at the output terminal.
Abstract: An electronic circuit comprising a comparator which is operated by a first power source voltage and having first and second input terminals, where the first input terminal is supplied with a reference voltage which is dependent on the first power source voltage, a detecting circuit for detecting a deviation of a second power source voltage and for outputting a control signal dependent on the deviation, where the first and second power source voltages undergo mutually independent deviations, and a voltage converting circuit supplied with an input signal for converting a voltage of the input signal depending on the control signal received from the detecting circuit. The voltage converting circuit supplies the input signal to the second input terminal of the comparator which outputs an error signal indicative of an error between the input signal voltage and the reference voltage.
February 22, 1995
Date of Patent:
August 20, 1996
Fujitsu Limited, Fujitsu VLSI Limited, Fujitsu Ten Limited
Abstract: A reference power supply includes an amplifier having an output terminal and a reference voltage source for providing the amplifier with a constant voltage. The amplifier amplifies the constant voltage to produce a load-driving reference voltage at the output terminal. The amplifier includes first and second constant current sources and a first transistor as an output transistor having an emitter connected to a high-potential power supply, a collector connected to the output terminal and a base connected to the second constant current source. A resistor circuit is provided between the collector of the first transistor and the low-potential power supply. The amplifier also includes first, second and third current mirror circuits. The first current mirror circuit has second and third transistors. The second transistor has an emitter connected to the resistor circuit and the third transistor has an emitter connected to the reference voltage source.
Abstract: A signal level converter is disclosed, for converting a signal having a first logic voltage swing characteristic to a signal having a second voltage swing characteristic. The converter comprises a level converting section and a differential circuit coupled thereto. The level converting section converts the supplied signal at the first logic voltage swing to an intermediate signal at a logic voltage swing different from the first voltage swing. The differential circuit 3, being supplied with the intermediate signal, produces an output signal at the second voltage swing level that corresponds to the potential difference between a high and low potential power supplies.
Abstract: A semiconductor memory has a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a differential sense amplifier, and load transistors. Each of the memory cells is a MIS transistor formed at each intersection of the word and bit lines. The threshold voltage of the MIS transistor is externally electrically controllable. The differential sense amplifier senses data stored in a selected memory cell located at an intersection of selected word and bit lines. A control pulse signal is applied to the gates of the load transistors, to bias the bit lines. The pulse width of the control pulse signal is a minimum essential to read data out of the selected memory cell. The control pulse signal controls the switching of the load transistors, to shorten a period during which a stress voltage is continuously applied to the drains of unselected memory cells that are connected to the bit line to which the selected memory cell is connected.
Abstract: A method of arranging components in a semiconductor device on a substrate (11), comprising provisionally determining a wiring path (3) so that a predetermined wiring capacitance is not exceeded in a specific network (1) and then performing a wiring process of elements (12) in the specific network within a component placement region (2) determined by the wiring path.
Abstract: A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.
Abstract: Disclosed is a data reading process as well as an improved semiconductor memory device. Input data supplied to the memory device is written in one of memory cells via a pair of bit lines when a write enable signal is active. After writing of the input data is completed, an equalizing circuit is activated to equalize the potential levels of bit lines used in data writing. An output circuit of the memory device is controlled such that the input data is forcibly output as output data from the memory device during the equalization immediately after writing of the input data is completed.
Abstract: Disclosed is a semiconductor memory device. A read control signal is externally input in read mode, and a test mode signal is externally input in a mode for testing memory cells. Based on the input read control signal, plural pieces of read data read out from a plurality of memory cells are latched by a plurality of latch circuits. Output signals of the latch circuits are input to a data compressor, which checks if the output signals of the latch circuits are the same and outputs a resultant signal in a form of compressed data of one bit. The output signal of the data compressor is input to an output circuit, which outputs the output signal of the data compressor based on the input test mode signal. A preset circuit allows the latch circuits to latch different pieces of data based on the test mode signal and the read control signal.
Abstract: An apparatus for determining power supply wirings of a semiconductor device includes a unit for executing a logic simulation based on both data concerning each of logic circuit blocks constituting the semiconductor device and data concerning signals for testing operations of the device, and thereby generating a respective output signal data for the logic circuit blocks, a unit for computing a respective operational frequency of the logic circuit blocks based on the generated output signal data, and a unit for computing a respective wiring width of each power supply line for supplying each of the logic circuit blocks with powers. The respective wiring width of each power supply line is determined based on the computed respective operational frequency of the logic circuit blocks and a plurality of wiring widths of respective power supply lines optimumly selected for each of a plurality of operational frequencies in advance.
Abstract: A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.
Abstract: A semiconductor memory device is disclosed, having a plurality of memory cells, from which cell data is read out, based on at least one control signal provided to the memory device. The memory device includes a transfer gate which receives read data from one of the memory cells, a latch circuit which latches the read data sent from the transfer gate, and an output buffer which outputs data produced in accordance with the latched read data. The memory device further includes a transfer gate controller, which produces a latch control signal based on the control signal and supplies the latch control signal to the transfer gate to control an ON/OFF action of the transfer gate. A delay circuit, incorporated in the gate controller, controls level-switching timing for the latch control signal such that after switching the level of the control signal, the transfer gate is turned off with a predetermined delay.
Abstract: In a detection circuit, a voltage-conversion circuit is supplied with a first voltage signal indicative of the state of an object circuit and produces an output current in response thereto, a detection circuit is supplied with a second voltage signal and detects the state of the object circuit in response thereto, and a clamping circuit, having an input terminal, is supplied at the input terminal thereof with the output current of the voltage-current conversion circuit and clamps the voltage at the input terminal thereof, and thus the output voltage of the voltage-current conversion circuit, at a predetermined level. The clamping circuit further produces the second voltage signal, which is supplied to the detection circuit, in response to the output current of the voltage-current conversion circuit and such that the second voltage signal has a magnitude proportional to the first voltage signal.
Abstract: Disclosed is a circuit which receives a supply voltage from a power supply and generates a voltage of a desired level different from that of the supply voltage. The circuit includes an oscillation circuit, a supply voltage generator, a first interconnection and a control circuit. The oscillation circuit generates an oscillation output signal. The supply voltage generator is responsive to the oscillation output signal from the oscillation circuit and generates a voltage of a predetermined level. The first interconnection connects the supply voltage generator to an internal circuit which is to be supplied with the voltage generated by the supply voltage generator. The internal circuit is also connected via a second interconnection to a power supply. The control circuit is provided between the first interconnection and the second interconnection as a variable resistor circuit which is responsive to the oscillation output signal from the oscillation circuit.