Abstract: A disc drive controller for controlling the transfer of data between a computer and a disc drive wherein it is possible to detect errors produced by the controller occurring in the writing or reading of data respectively to and from a disc drive. Error detection occurs according to the detection of data modulated by a write data circuit or the lack thereof.
Abstract: The DC-DC converter is disclosed, which has an output terminal connected to an external load, and produces a desired output voltage at the output terminal. An output capacitor in the converter has a first electrode connected to the output terminal and a second electrode. The charge/discharge regulator controls electrical connection between a DC power supply and the output capacitor to permit the capacitor to be charged or discharged. The DC-DC converter includes a first detecting circuit for detecting a change in the output voltage at the output terminal, and a second detecting circuit for detecting a variable load current flowing into the converter from the load via the output terminal.
Abstract: An input protection circuit includes a conductor pattern extending from a first end connected to an input pad to a second end connected to an integrated circuit, first and second, mutually separated ground patterns disposed at both sides of the conductor pattern with a separation therefrom, a first gate pattern provided on a gap between the conductor pattern and the first ground pattern, and a second gate pattern provided on a gap between the conductor pattern and the second ground pattern, wherein the conductor pattern, the first ground pattern and the first gate pattern form a first transistor extending continuously from the first end to the second end of the conductor pattern at a first side of the conductor pattern, and wherein the conductor pattern, the second ground pattern and the second gate pattern form a second transistor extending continuously from the first end to the second end of the conductor pattern at a second side of the conductor pattern.
Abstract: Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source.
Abstract: A method is disclosed for verifying accurate writing of data onto a recording medium such as a disk. Data, provided to be written on the disk, is written onto the disk. The data written on the disk is read out from the disk. A user data portion in the data to be written on the disk is compared with a user data portion in the data read from the disk, so as to count a first number of errors between the both user data portions. An error correction on the data read from the disk is performed to count a second number of errors with respect to the user data portion in the read data. By comparing the first number of errors with the second number of errors, it is determined if data writing on the disk has been accomplished properly.
Abstract: An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells is provided. The disclosed device protects against reading faults even in the event that adjacent transistors may be over erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word line is selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over erased condition.
Abstract: A method of manufacturing a semiconductor device capable of isolating fine pattern elements by using LOCOS. The method includes the steps of: (a) forming a relatively thick first nitride film pattern on the surface of a semiconductor substrate having an oxide film; (b) wet-etching the oxide film by using the first nitride film as a mask; (c) filling the under-etch region of the first nitride film with nitride and forming a second nitride film thinner than the first nitride film on the exposed surface of the semiconductor substrate; (d) thermally oxidizing all the exposed second nitride film in a dry oxygen atmosphere to form an oxide film on the surface of the semiconductor substrate at least at the region not covered with tile first nitride film; and (e) forming a thermal oxide film on the semiconductor substrate not covered with the first nitride film at a temperature lower than the oxidation temperature at the step (d).
Abstract: A load generator is disclosed, which controls the voltage swing of the complementary logic signals generated in a semiconductor memory device. The load generator includes a first load circuit for controlling the potential levels of the signals appearing on a pair of complementary input signal lines. The first load circuit includes a first and second voltage dividers connected to the complementary input signal lines. Each of the first and second voltage dividers include a first voltage dividing transistor and a first voltage dividing resistive element connected in series between the semiconductor's low and high potential power supplies. The two first voltage dividing transistors are connected to each other in such a manner that a voltage, divided by one of the two transistors, is applied to the gate of the other transistor. The load generator further includes a second load circuit for controlling the potential levels of the signals appearing on a pair of complementary output signal lines.
Abstract: A system and apparatus for using hierarchically organized data to design semiconductor integrated circuits is herein disclosed wherein a plurality of macros and circuit logic cells containing circuit component parameter information are cross referenced using two types of pointers. An intermediate table 27 in a logic development file 5 stores information relating to a general controlling macro "CHIP", user defined macros A, B, and also stores the parameter information relating to every macro. A cell table 28 stores circuit cells C, D, E, F. The macro "CHIP" A, B, and cells, and the macro and cell are cross referenced by multi-table and an identical table pointer.
Abstract: An electron-beam exposure system includes an astigmatic compensation circuit that increases a voltage applied across a pair of electrodes forming an electrostatic sub-deflector and simultaneously decreases a voltage applied across another pair of electrodes forming the same electrostatic sub-deflector with a same magnitude as in the case of increasing the voltage, wherein the magnitude of the voltage change is changed in response to the deflection of the electron-beam caused by a main deflector.
Abstract: An input signal is provided at first input terminals of a plurality of parallel AND gates in a delay time control circuit. A digital signal from a decoder having a plurality of bits is coupled to second input terminals of the AND gates with one bit coupled per AND gate. The decoder outputs a signal having an a high level in response to an external input control signal. Output signals from the AND gates are coupled to inputs of a plurality of serially connected OR gates.
Abstract: A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).
Abstract: A charged particle beam exposure system checks for the shape of the charged particle beam shaped by a mask by causing a scanning of a marker pattern provided on a substrate along a scanning path. The reflected electrons emitted from the substrate are detected, and the shape of the charged particle beam is obtained based upon the profile of the reflected electrons along the scanning path. By comparing expected pattern of the reflected charged particles, one can detect anomaly in the beam shaping aperture on the mask, wherein the step for comparing the observed pattern and the expected pattern includes a step of pattern matching for shifting the patterns with each other for seeking a minimum of unoverlapped area of the patterns. When the difference between the observed pattern and the expected pattern exceeds a threshold in the state that the unoverlapped area is minimized, an alarm produced with the information indicative of the location of the pattern wherein the threshold has been exceeded.
Abstract: A first selector outputs either an output of an ALU (arithmetic logic unit) or a first clipped value to a first bus. A temporary register holds the output signal of the ALU, and a second selector outputs either the output signal of the temporary register or a second clipped value. A controller causes an operation result regarding lower data of first and second operands to be stored in the temporary register in a first cycle of the ALU when each of the first and second operands consists of 2n bits while the ALU operates on n bits per cycle thereof. When an operation result regarding upper data of the first and second operands overflows in a second cycle of the ALU, the controller causes the first and second selectors to output the first and second clipped values. When the operation result regarding the upper data does not overflow, the controller causes the first and second selector to respectively output the output signals of the ALU and the temporary register.
Abstract: An output circuit, having a plurality of bipolar transistors for driving a CMOS circuit, comprises an output level maintaining transistor connected between an output terminal of the output circuit and ground. The output level maintaining transistor maintains a level of the output terminal at a specific high potential by transmitting a current from the output terminal to the ground when the output circuit is outputting a high level signal to the output terminal, and the output level maintaining transistor is cut OFF when the output circuit is outputting a low level signal to the output terminal. Consequently, the output circuit according to the present invention reduces power consumption of the output circuit and avoids erroneous operation of the CMOS circuit.
Abstract: A nonvolatile semiconductor memory device has a plurality of word lines, a plurality of bit lines, a plurality of nonvolatile memory cells, and a source power supply circuit. Each of the nonvolatile memory cells is formed of a MIS transistor disposed at each intersection of the word lines and the bit lines, and a threshold voltage of the MIS transistor is externally electrically controllable. The source power supply circuit, which is connected to sources of the nonvolatile memory cells, is used to apply a first voltage to the sources of the nonvolatile memory cells to negate an influence caused by an over-erase phenomenon at the time of a reading operation.
Abstract: A semiconductor memory is set in a required operation mode according to an external instruction. The memory properly controls the activation timing of a sense amplifier (1) incorporated in the memory. The memory is capable of surely amplifying a voltage difference between bit lines in every operation mode with no delay in access time, to achieve a high-speed operation.The memory has the sense amplifier (1) for detecting and amplifying a voltage difference between complementary bit lines that transfer data to and from a corresponding memory cell, and a unit (2) for changing the activation timing of the sense amplifier according to an externally instructed operation mode (C).
Abstract: An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.
Abstract: A wafer-scale semiconductor integrated circuit device includes a wafer, a plurality of chips formed on the wafer, each of the chips having an internal logic circuit, interconnection lines mutually connecting the chips, and clamping circuits which are coupled to chips from among the chips which are located at a periphery of an arrangement of the chips and which prevent the interconnection lines related to the chips located at the periphery from being in a floating state.