Abstract: An output circuit comprises first and second transistors connected in series between a first voltage source and an second voltage source such that the first and second transistors are turned on and turned off respectively in response to an input logic signal and a logic inversion thereof, third and fourth transistors connected in series between a third voltage source and fourth voltage source such that the third and fourth transistors are turned on and turned off respectively in response to the logic inversion of the input logic signal and the input logic signal, first and second power transistors connected in series between a fifth voltage source and a sixth voltage source such that the first power transistor is turned on in response to the turning-on of the first transistor and turned off in response to the turning-on of the second transistor, the second power transistor is turned on in response to the turning-on of the third transistor and turned off in response to the turning-on of the fourth transistor,

Abstract: A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a serial data register which includes a number of bit cells corresponding to one word of the memory cell array, a decoder for decoding an address signal and for successively making an access to each bit cell of the serial data register based on a decoded result, a register group comprising m+1 shift registers in correspondence with each digit of the address signal, where each of the shift registers comprise n registers which are connected to form a loop and m and n are integers satisfying m.gtoreq.

Abstract: A semiconductor memory device includes a RAM and a serial access memory (SAM). The SAM includes an address counter which generates a slave address and a master address. The slave address precedes the master address by half the period of a serial access strobe signal. A redundancy decision is made by comparing the slave address with a redundancy address. When the master address is supplied to a data register provided in the SAM, the decision result is available. That is, the SAM can be accessed immediately after the master address is supplied thereto.

Abstract: A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected in series between the output terminal and another power source line, the first and the second switching transistors operating in a complementary manner in response to an input signal, one or more nodes of each switching transistor being connected by one or more current paths each connecting at least one capacitor, whereby an input signal is transmitted to the output terminal at a specified interval defined by the capacitance of the capacitor.

Abstract: A semiconductor device includes a semiconductor chip, a substrate for supporting the semiconductor chip, a plurality of terminals provided on the substrate for external connections, a plurality of lead wires provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure includes at least a lower conductor layer provided on the substrate and patterned into a plurality of pattern portions connected electrically to the terminals, an insulator layer provided on the lower conductor layer, and an upper conductor layer provided above the insulator layer.

Abstract: A programmable logic device includes: a programmable AND array; an OR array operatively connected to the AND array; a plurality of external terminals; and a plurality of cell blocks operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.

Abstract: A PLL synthesizer includes a voltage-controlled oscillator generating an output signal having a frequency based on a first signal supplied thereto, a PLL control circuit which generates a second signal based on the output signal and a set frequency, a lowpass filter having an input terminal and an output terminal, for filtering the second signal supplied through the input terminal to thereby generate the first signal supplied to the voltage-controlled oscillator through the output terminal, and a switch circuit which is coupled between the input and output terminals of the lowpass filter and which supplies the second signal directly to the voltage-controlled oscillator during a predetermined time when the set frequency is changed.

Abstract: A pattern data processing method processes hierarchical pattern data which has a hierarchical structure and describes in each level thereof one or a plurality of internal cells constituting one or a plurality of logic blocks of a semiconductor integrated circuit device which is to be produced. The pattern processing method comprises the steps of defining a frame at a boundary between a level i of the hierarchical structure and a level i+1 which is higher than the level i, cutting a first portion of a pattern which protrudes out of the frame form the level i to the level i+1 and defining the cut, first portion as a pattern of the level i+1, cutting a second portion of a pattern which protrudes out of the frame from the level i+1 to the level i and deleting the cut, second portion, and repeating the steps of cutting the first and second portions for a predetermined number of levels for increasing values of i, where i=1, 2, . . .

Abstract: An output buffer circuit includes a prestage circuit which generates a first potential and a second potential (an intermediate voltage) based on the voltage of an input signal. The first potential is higher than the second potential. A final-stage circuit generates an output signal by controlling a current passing therethrough from a power source on the basis of the potential of the input terminal. The output signal is supplied to an ECL circuit through the output terminal. A control circuit generates a control signal during a predetermined time when a change in voltage of the input signal occurs. A bypass circuit sets the potential of the input terminal of the final-stage circuit lower than the second potential and discharging a parasitic capacitance coupled to the input terminal during the predetermined time defined by the control signal supplied from the control circuit when the prestage circuit outputs the second potential in response to a change in voltage of the input signal.

Abstract: A digital-to-analog converter includes a ladder type resistor network having stages equal in number to bits of a digital input signal, each of the stages including a first resistor and a second resistor mutually connected in series via a node. A first switch, which is provided for each of the stages, selectively supplies either an upper limit voltage or a lower limit voltage to a corresponding one of the stages in accordance with a logical value of a corresponding one of the bits of the digital input signal. An analog signal output terminal is coupled to the node of one of the stages which corresponds to a most significant bit of the digital input signal. An analog output signal is output via the analog signal output terminal. An offset level control resistor has a first end connected to the node of one of the stages which corresponds to a least significant bit of the digital input signal and a second end.

Abstract: An integrated circuit device includes a package having first and second surfaces and first and second internal connection lines. A semiconductor integrated circuit chip is mounted on the first surface of the package. A first group of external connection terminals is provided on the first surface of the package, and is electrically connected to the semiconductor integrated circuit chip through the first internal connection lines. A second group of external connection terminals is provided on the second surface of the package so as to form a matrix arrangement of terminals, and is electrically connected to the semiconductor integrated circuit chip through the second internal connection lines. The second group of external connection terminals includes specific terminals specifically passing signals to be supplied to or from the semiconductor integrated circuit chip. The signals passing through the specific terminals are signals used at the time of evaluating the semiconductor integrated circuit chip.

Abstract: A bias voltage supplying circuit for supplying a bias voltage includes first and second PNP type transistors having emitters coupled to a first power source terminal and bases connected to each other, where the first PNP type transistor has a collector coupled to the base thereof, first and second NPN type transistors having collectors respectively connected to collectors of the first and second PNP type transistors, emitters coupled to a second power source terminal and bases connected to each other, where the second NPN type transistor has the collector connected to the base thereof, and a diode part coupled between the emitter of the second PNP type transistor and the base of the second NPN type transistor. The diode part has an anode end coupled to the emitter of the second PNP type transistor and a cathode end coupled to the base of the second NPN type transistor, and the diode part has a forward voltage drop V.sub.D which is less than a voltage V.sub.S across the first and second power source terminals.

Abstract: A memory card is used on a card write and/or read apparatus which has a data bus with an arbitrary bit width and writes and/or reads a datum to and/or from the memory card.

Abstract: A semiconductor memory includes a random access memory (RAM) and a serial access memory (SAM). The RAM includes a memory cell array including memory cells.

Abstract: An amplifier circuit comprises a variable gain amplifier for receiving an input signal which is to be amplified by the amplifier circuit with a variable gain. The variable gain is controlled by a control signal. The amplifier circuit also includes a constant gain amplifier for amplifying a signal outputted from the variable gain amplifier with a constant gain, and a gain control circuit responsive to a signal outputted from the constant gain amplifier so as to supply the control signal to the variable gain amplifier. The signal from the constant gain amplifier is outputted as an output signal of the amplifier circuit, and the gain control circuit generates the control signal during a time period in which a level of the output signal of the constant gain amplifier is higher than a reference level which is a predetermined value lower than a peak value of the output signal of the constant gain amplifier.

Abstract: A dynamic random access memory including: a memory constituted by a plurality of dynamic type memory cells; a refresh control circuit for refreshing the memory cells by controlling a refresh address circuit in a refresh mode; an address latch circuit for latching an external address signal in a read/write mode and latching a refresh address signal in the refresh mode; a clock generating circuit for generating a second clock and a third clock based on a first clock obtained after a predetermined delay time from a trailing edge of a row address strobe signal, the second clock controlling a first timing for taking the external address signal into the address latch circuit in the read/write mode, and the third clock is generated after the second clock and controls a second timing for taking the refresh address signal into the address latch circuit in the refresh mode.

Abstract: A constant voltage source circuit which is provided with an output transistor (Q.sub.1) for outputting a predetermined output voltage (V.sub.0) in accordance with an input voltage (V.sub.IN) and a differential amplifier (A), and is further characterized in that the circuit further comprises a reference voltage control means which monitors variations of the input voltage (V.sub.IN) and outputs a predetermined constant voltage to the differential amplifier (A) as a reference voltage when the input voltage (V.sub.IN) is higher than, a predetermined voltage level, and a voltage varied in accordance with the variation of the input voltage (V.sub.IN) is output therefrom to the differential amplifier (A) as a reference voltage when the input voltage (V.sub.IN) falls below a predetermined voltage level.

Abstract: A method of fabricating a semiconductor device comprises steps of accommodating a substrate on which the semiconductor device is to be fabricated in a container of an electrically insulating material, forming a film of a volatile organic solvent such that the film covers substantially an entire surface of the container and the substrate accommodated therein, said step of forming the film being performed while maintaining a connection between the film of the volatile organic solvent covering the surface of the container and the ground, so that electric charges are eliminated from the substrate and the container by flowing to the ground, and removing the film of the volatile organic solvent by evaporating the solvent.

Abstract: A connecting structure for connecting conductors used for wiring in a semiconductor device comprises a first conductor provided on a part of the semiconductor device for passing the flow of electrons, an insulator provided on the first conductor and formed with a contact hole, and a second conductor provided on the insulator for passing the flow of electrons, in which the second conductor is provided so as to sandwich the insulator together with a part of the first conductor. The first and second conductors are contacted to each other across the insulator at the contact hole so that the electrons flow through the contact hole. The contact hole extends in a general direction of a flow of electrons passing therethrough and has a stepped shape in which a width measured perpendicularly to the general direction of the flow of electrons increases stepwise towards the general direction of the flow of electrons.

Abstract: A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage.