Abstract: A D/A converter includes a D/A conversion part for converting a digital input signal into an analog output signal, a parameter setting part for generating a plurality of circuit parameters which define a voltage range of the analog output signal, and a setting control part for selecting desired circuit parameters from the plurality of circuit parameters in accordance with data supplied from an external device, so that the D/A conversion part generates the analog output signal having a voltage based on the desired circuit parameters.

Abstract: A current mirror amplifier circuit includes a differential amplifier circuit having first and second nodes for differentially amplifying a pair of complementary input signals in an activation mode. A current mirror circuit is coupled between a first power source and the first and second nodes of the differential amplifier circuit. A switching circuit is coupled between the differential amplifier circuit and a second power source which supplies a second voltage lower than a first voltage supplied by the first power source for switching a mode of the differential amplifier circuit from a standby mode to the activation mode in response to an activation signal. A circuit is coupled between the first power source and the first and second nodes of the differential amplifier circuit for pulling up potentials of the first and second nodes during the standby mode. This circuit is deactivated after the differential amplifier circuit is switched from the standby mode to the activation mode.

Abstract: A multiplexer circuit comprises a plurality of voltage generation circuits which produce corresponding output voltages having respective, different voltage levels in accordance with an ordered sequence thereof, from the lowest to the highest level. The outputs of the plurality of voltage generation circuits are supplied to a common output line. A decoder circuit receives a control data input signal which designates a selected one of the plurality of levels of the output signal and produces a signal for disabling each of the voltage generating circuits having an output voltage level of a higher order than that of the voltage generating circuit producing the output voltage of the selected level designated by the control data input signal. Voltage generating circuits of lower order need not be disabled.

Abstract: A semiconductor memory device comprises a first memory comprising memory cells for prestoring fixed data, a decoder for decoding an input address and for reading out a fixed data from the first memory based on a decoded input address, a second memory for storing a data identical to that prestored in a defective memory cell of the first memory, where the second memory comprising programmable non-volatile memory cells, a discriminating part including a third memory for storing a redundant address of each defective memory cell of the first memory for discriminating whether or not the input address coincides with the redundant address and for outputting a discrimination signal when the input address coincides with the redundant address, and a selecting part supplied with data read out from the first and second memories for normally outputting the data read out from the first memory and selectively outputting the data from the second memory when the discrimination signal is received from the discriminating part.

Abstract: A method for fabricating a semiconductor device comprises the steps of cleaning a semiconductor substrate in a cleaning liquid essentially consisted of a mixture of an ammonia water having a composition of 29 percent by weight, a hydrogen peroxide aqueous solution having a composition of 31 percent by weight and a deionized water. The cleaning liquid contains the ammonia water and the hydrogen peroxide aqueous solution with respective volume parts such that the volume part of the ammonia is set equal to or smaller than 30 parts with respect to the deionized water of 1000 parts, the volume part of the ammonia water is set equal to or smaller than the volume part of the hydrogen peroxide aqueous solution, and the volume part of the hydrogen peroxide aqueous solution is set equal to or smaller than 100 parts with respect to the deionized water of 1000 parts. The volume part of the hydrogen peroxide aqueous solution is further set equal to or smaller than a boundary composition Y2 represented asY.sub.2 =0.25 X.

Abstract: Where an electrically erasable and programmable non-volatile semiconductor memory element (EEPROM cell) for storing a setting and releasing of the software data protection has already been set in the logic state designating the software data protection setting state, and operation of setting the logical state designating the software data protection setting is not applied to the EEPROM cell even if the address and data for setting the software data protection is input. Further, where the logic state designating the releasing of the software data protection has been set in the electrically erasable and programmable non-volatile semiconductor memory element, the operation of setting the logical state designating the release of the software data protection is not set to the EEPROM cell, even if the address and the data for releasing the software data protection is input.

Abstract: An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.

Abstract: A PLL synthesizer circuit includes a lowpass filter including capacitors for restricting an output voltage of the lowpass filter, a charge pump circuit for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter, a voltage controlled oscillator for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter, a frequency divider for frequency-dividing the output signal of the voltage controlled oscillator to output a comparison signal and having a variable frequency dividing ratio, a phase comparator for comparing a phase of a reference signal having a predetermined frequency and a phase of the comparison signal output from the frequency divider to output phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal, and a charge pump control circuit for forming control information based on the phase error information when switching

Abstract: A signal converter includes a frequency-to-voltage converter for converting a frequency of an input signal received via an input terminal into a control voltage. The input signal contains a noise signal having a frequency different from the frequency of the input signal. The control voltage changes in accordance with a change of the frequency of the input signal. A filter has a variable cutoff frequency so that the noise signal is eliminated from the input signal and outputs a filtered signal. The variable cutoff frequency is changed in accordance with a change of the control voltage so that a change of the variable cutoff frequency follows a change of the frequency of the input signal. A comparator compares the filtered signal with a reference voltage and converts the filtered signal into a pulse signal having a pulse width corresponding to the frequency of the input signal.

Abstract: A circuit has a level converting circuit for converting a signal having level in conformance with a first logic system into a signal having a level in conformance with a second logic system.

Abstract: In a method of manufacturing reticules of the present invention, device pattern data is generated by shrinking (or magnifying) the pregenerated device pattern by calculation with determined shrinking ratio and meanwhile it is combined with alignment mark data of pregenerated alignment mark pattern in the determined shape and size and the combined data is then converted to the exposure data. As a result, in generating the reticule by shrinking the device pattern, a reticule having no positional displacement between the device pattern and alignment mark pattern can be easily generated in high efficiency.

Abstract: A receiver circuit includes a first amplifier for amplifying an input signal and for outputting a first amplified signal, a first bias circuit coupled to the first amplifier for supplying a first bias current to the first amplifier, where the first amplifier and the first bias circuit form a first circuit part, a second amplifier coupled to the first amplifier for amplifying the first amplified signal output from the first amplifier and for outputting a second amplified signal as an output signal of the receiver circuit, and a second bias circuit coupled to the second amplifier for supplying a second bias current to the second amplifier, where the second amplifier and the second bias circuit form a second circuit part, and the first and second bias circuits are independent of each other and have mutually opposite temperature characteristics so that the first and second bias currents respectively change in mutually opposite directions with increasing ambient temperature, to thereby suppress a change in current

Abstract: A semiconductor integrated circuit device includes a bias generating circuit having an operational amplifier connected to receive an input voltage at its inverting input terminal to produce a gate voltage. A field transistor has its gate connected to receive the gate voltage from the operational amplifier and its drain connected to a resistor and to an noninverting input terminal of the operational amplifer. A field effect transistor has its gate connected to receive the gate voltage from the operational amplifier to produce a current corresponding to the input voltage. One group of current source is responsive to an output voltage of the bias generating circuit to produce a plurality of currents of an equal magnitude and one switching circuit is responsive to an input digital value to selectively output the currents from the group of current sources to its common output.

Abstract: A semiconductor memory device with a flash write function includes word lines and bit lines; memory cells connected between the word lines and the bit lines; and a flash write mode designating unit for designating a flash write mode in accordance with external control signals. The semiconductor memory device further includes an internal address generating unit which is driven during a flash write mode for sequentially generating internal address signals. The semiconductor memory device additionally has a word-line selecting unit for sequentially selecting the word lines in accordance with the internal address signals from the internal address generating unit. A preset data generating unit is further included in the semiconductor memory device for generating preset data.

Abstract: An integrated circuit includes a circuit chip, one or more circuits provided on the circuit chip, an input/output circuit provided on the circuit chip in electrical connection to the one or more circuits for transmitting and/or receiving an information signal to and from an external circuit outside the circuit chip, a plurality of resistance areas provided on the circuit chip for electrical connnection therewith for providing a predetermined input and/or output impedance of the integrated circuit, and a plurality of connection pads provided on the circuit chip in correspondence to the plurality of resistance areas for electrical connection therewith, for electrical connection to the external circuit. The plurality of resistance areas include a plurality of elongated resistance strips connected in series and extending parallel with each other, wherein each elongated resistance strip in each resistance area extends on the major surface of the circuit chip in a predetermined direction.

Abstract: An integrated circuit device formed on a chip includes a pair of signal input terminals, a signal discriminating circuit having a pair of input terminals coupled to the signal input terminals, for comparing a data signal and a reference signal supplied through the input terminals and for determining whether or not the level of said data signal is higher than that of said reference signal, a pair of test signal terminals to which a predetermined voltage is applied, and a voltage dividing circuit for dividing the predetermined voltage to thereby generate a test signal to be supplied to the signal discriminating circuit through the input terminals.

Abstract: A level changing semiconductor integrated circuit includes two current paths in which emitters of first and second bipolar transistors are each connected in series to one terminal of first and second MOSFETs, respectively. The current paths are disposed between a high-potential power source and a low-potential power source. Gates of the first and second MOSFETs are cross-connected to the emitters of the bipolar transistors of opposite current paths. The emitters of the first and second bipolar transistors provide output signals. At least two different types of input signals having different signal levels are simultaneously applied to respective input units of the current paths.

Abstract: A logic operation circuit includes an instruction signal generating circuit for generating an instruction signal which designates a bit of a predetermined n-bit code signal in accordance with a combination of a first input logical numeral and a second input logical numeral. The logic operation circuit also includes a bit selecting circuit for selecting said bit designated by the instruction signal generated by the instruction signal generating circuit and for outputting the selected bit as an output logical numeral.

Abstract: A multi-port semiconductor memory includes a memory cell array having a plurality of memory cells (10), a plurality of columns and rows, a write/read system, and at least one read system having sense amplifiers, each of the columns having a pair of data lines. Each of the sense amplifiers has first and second terminals connected to the pair of data lines and senses a voltage difference between the first and second terminals. The multi-port semiconductor memory also includes an address coincidence detection circuit which generates a control signal when a first address provided for writing write data into the memory cell array by the write/read system coincides with a second address provided for reading the write data by the read system.

Abstract: An input signal is received by a level shift circuit to generate a plurality of level-shifted output signals which have different shift amounts to each other. A switch circuit, selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from the level-shifted output signals when the logic level of the input signals indicates a second level.