Abstract: A coding/decoding part performs codes and decodes a given signal in one of a plurality of coding/decoding modes of different bit rates; and a control part sets a predetermined bit rate to be applied by the coding/decoding part in case a given signal is output after being coded and decoded by said coding/decoding part without storage thereof in a predetermined recording medium.

Abstract: A multilayer wiring structure for MMICs includes a power-supply wiring formed of a multilayer wiring (a plurality of power-supply lines). The wires are interconnected by throughholes. A power-supply current is divided and supplied to the lines. A large current can be supplied to the entirety of the multilayer wiring, even when the width of each of the lines is reduced. The multilayer wiring structure has an improved degree of freedom in the layout of wiring.

Abstract: A magneto-optical storage medium that protects against the effects of cross-talk, making it possible to further reduce the level of track density, and which also makes it possible to conduct high-density recording/playback with a reduced magnetic field for erasure and a favorable level of playback signal quality. More specifically, a magneto-optical storage medium, which includes at least the following laminated layers, in the following order: a playback layer, a non-magnetic layer, a transfer layer, a cut-off layer, and a recording layer. The playback layer preferably displays easy in-plane magnetization characteristics within the monolayer at room temperature, and the transfer layer and the recording layer each have easy magnetization characteristics in the vertical direction of the monolayers at room temperature when each layer is considered as a monolayer.

Abstract: An apparatus has a main display screen and an auxiliary display screen being smaller in size than the main display screen, and a received mail is displayed on a scroll basis on the auxiliary display screen and is outputted in form of a voice reading aloud the received mail in synchronism with the display.

Abstract: In a printer connected to a network, a mail server, having an address inherent in the printer, for transmitting/receiving an electronic mail is arranged. The electronic mail received by the mail server is decoded by a mail process unit. When an electronic mail sentence includes a control instruction of power supply control related to the printer, a request for a report of printer supplies management information, a request for a report of an operation state check, updating of a firmware, maintenance, printing of an attached file, or the like, a process depending on the control instruction is executed.

Abstract: A structure for eliminating the influence of an antenna line connected to the patch electrode on the antenna characteristics of a patch antenna built in an MMIC is disclosed. A through-hole is formed in the antenna ground plane which is provided under the patch electrode with an interlayer insulation film therebetween, the antena line is provided in the side opposite to the patch electrode with respect to the antena ground plane, and the patch electrode and antenna line are connected to each other with a conductor passing through the trough-hole.

Abstract: A packet processing unit and a session managing unit, which are conventionally arranged in a server, are arranged in a network connecting device, and the network connecting device performs a packet relay process based on session management. As a result, the load on a server is reduced, and a process by the server is performed faster.

Abstract: A semiconductor device having; a semiconductor substrate having first and second regions defined in a principal surface of the semiconductor substrate; a first underlying film formed in the second region; a first lamination structure formed in a partial area of the first region, the first lamination structure having a conductive film and an insulating film stacked in this order from the substrate side; and a second lamination structure formed on the first underlying film and having a conductive film and an insulating film stacked in this order from the substrate side, wherein the insulating films of the first and second lamination structures are made of the same material and the height of the upper surface of the second lamination structure as measured from the principal surface of the semiconductor substrate is equal to or lower than the height of the upper surface of the first lamination structure as measured from the principal surface of the semiconductor substrate.

Abstract: An image reading apparatus including an image reading section, an amount-of-movement detecting thinning out the transfer data other than particular transfer data, each of successive transfer data pieces at a time, adding the amount of movement, which is contained in the thinned-out transfer data, to the amount of movement, which is contained in the particular transfer data, and generating compressed data composed of the image data in the particular transfer data and the added amount of movement, and a data transferring section for transferring one of the transfer data and the compressed data to a destination.

Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: In a method for managing a skill of a learner, it is determined based on an obtained date when the learner obtained the skill, whether or not the skill obtained by the learner passes a valid term, and a skill level is changed based on a result.

Abstract: A method of switching the mode of a PLL circuit which has a high-speed mode and a normal mode, which allows the PLL circuit to be locked up at a high speed. The PLL circuit includes a phase comparator and a charge pump for generating a current depending on a comparison output signal from the phase comparator. The mode switching method includes the steps of detecting whether a current output terminal of the charge pump is in a high impedance state, and switching the mode of the PLL circuit from the high-speed mode to the normal mode or from the normal mode to the high-speed mode when the high impedance state is detected.

Abstract: Disclosed is the purchase information collecting method capable of collecting reliable purchase information about any kind of commodity using a network. In the purchase information collecting method, used is a server apparatus capable of communicating with a computer managed (operated) by a seller and a computer operated by a purchasers, stores, when receiving sales information that is capable of identifying a deal about a commodity and is generated and transmitted by the computer managed by the seller, the received sales information on the first storing part.

Abstract: NMOS transistors N3 and N3S are connected in series between a PMOS transistor P1 and an NMOS transistor N1S constituting a first inverter connected between a power supply potential VDD2, which satisfies VDD1<VDD2, and a ground potential VSS, and likewise, NMOS transistors N4 and N4S are connected in series between a PMOS transistor P2 and an NMOS transistor N2S constituting a second inverter. The gate insulating films of the MOS transistors P1, P2, N3 and N4 are thicker than those of the transistors N1S and N4S. The gates of the NMOS transistors N3 and N4 are connected to VDD2, the gates of NMOS transistors N3S and N4S are connected to VDD1 and these transistors are constantly on.

Abstract: A high frequency semiconductor device has at least one gap which is formed by removing part of a ground plate under an inductor. By forming the gap, a parasitic capacitance which is caused by a dielectric layer between the ground plate and the ground potential can be deleted.

Abstract: The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22 and which includes a larger layer number of insulation films 24, 26 28 covering the side wall of the interconnection layer 14 at the side wall of the cap insulation film 22 than a layer number of insulation films 24, 26 at the side wall of the cap insulation film 22. Accordingly, the sidewall insulation film can be thickened at the side wall of the interconnection layer 14, whereby a parasitic capacitance between the interconnection layer 14 and the electrodes 32 adjacent to the interconnection layer 14 through the sidewall insulation film can be low.

Abstract: A knowledge information managing apparatus manages knowledge information to reuse information of analytical details and a process which have led to information as a fruit. The knowledge information managing apparatus accumulates dialogue streams including the contents of a series of message data exchanged between persons involved in a business through a network. The knowledge information managing apparatus also sequentially accumulates objects required to perform the business in a process from generation of the problem to a conclusion about the problem, in a state in which the objects are required. The knowledge information managing apparatus relates a desired one of the accumulated dialogue streams and a desired one of the accumulated objects to each other in response to a relating request, and outputs information about the desired dialogue stream and the desired object which are related to each other in response to a related information acquiring request.

Abstract: An address generating circuit having: a first switch transistor, a second switch transistor, a fuse element, and a power-ON reset circuit for outputting a first reset signal for controlling ON/OFF conditions of the first switch transistor and a second reset signal for controlling ON/OFF conditions of the second switch transistor. The address generating circuit also includes a latch circuit for latching and outputting a predetermined potential corresponding to a cut-off or a no cut-off condition of the fuse element. The first reset signal turns ON the first switch transistor during a first period immediately after the power supply is turned ON and always holds the first switch transistor in the OFF condition after the first period is completed. Furthermore, the second reset signal turns ON the second switch transistor at least during a second period after the first period and always holds the second switch transistor in the OFF condition after the second period is completed.

Abstract: A read processing method and a reproduction system for continuously reading out an audio/visual data from a storage medium (2). When a data cannot be read out from storage medium (2), a data having a predetermined pattern is transferred so as to prevent operational deadlock caused by an error data even when the audio/visual data is transferred continuously. This method enables to allow to transfer audio/visual data continuously. Also, an application (1) for reproducing data enables to identify an error, enabling to avoid the application (1) falling into a non-executable condition or the system falling into a hung-up condition. In addition, because whether a retry is needed is determined when error data is transferred, it becomes possible to avoid an unnecessary retry in reproducing audio/visual or the like.

Abstract: A semiconductor memory device includes a data buffer for inputting/outputting data from/to an exterior of the device, a plurality of DRAM cell array blocks, an SRAM redundancy cell which is situated around each of the plurality of DRAM cell array blocks, a fuse circuit which stores therein an address of a defect memory cell in the DRAM cell array blocks, a comparison circuit which compares an input address with the address stored in the fuse circuit, and an I/O bus which couple the SRAM redundancy cell to the data buffer in response to an address match found by the comparison circuit.