Abstract: A work conveying and transferring apparatus has a trolley having a casing defining a hermetically sealed space, and a support portion provided on the trolley for placing at least one container containing a cassette carrying works. A container opening device is provided on the trolley to open the container placed on the support portion, and a cassette transferring device is provided for transferring the cassette from the trolley to a treating apparatus, with the container placed on the support portion opened. The support portion is provided in the sealed space, and works can be double sealed by the sealed space and the container.

Abstract: An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals.

Abstract: A memory control system employing at least one clock synchronous memory which is controlled by a memory control unit includes an interface circuit. The interface circuit functions as an output buffer synchronous with a clock. Thus, the interface circuit holds a memory control signal, which is output from the memory control unit for controlling the memory, and transmits the memory control signal to the memory in the predetermined time. In this configuration, access to the memory is made in consideration of the delay time required for a memory control signal to reach the memory via the interface circuit. Preferably, the presence or absence of the interface circuit for holding a memory control signal is determined based on an operation mode in which the memory control unit is established. Further proposed is a memory control method for controlling at least one clock synchronous memory which is implemented in the memory control system.

Abstract: According to the present invention, a receiving apparatus of a code spread communication type according to this invention includes a reception unit for receiving a transmitted signal; a demodulation signal generator for performing orthogonal modulation on a spreading code assigned to a communication channel, generating a reciprocal of a complex signal undergone the orthogonal modulation, and multiplying the reciprocal of the complex signal by a local frequency signal to generate a demodulation signal; and a first multiplier for multiplying the transmitted signal, received at the reception unit, by the demodulation signal to perform spread demodulation and orthogonal demodulation. With this structure, spread demodulation and orthogonal demodulation can be performed simultaneously by multiplying a reception signal of a high frequency by the aforementioned demodulation signal.

Abstract: A decoder circuit includes a detecting device which detects a selecting signal for selecting the decoder circuit, a clock-signal supplying device which supplies a clock signal, and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when the detecting device detects the selecting signal.

Abstract: The present invention relates to a magnetic disk control unit which can accomplish active interchange of firmwares. Thus, in this invention, a firmware constituting the magnetic disk control unit includes an internal table area for retaining various data necessary for control, a save area for temporarily saving, of the data in the internal table area, data necessary before and after interchange of the firmware while the firmware undergoes active interchange, a first interruption control section serving, as interruption handling functions, a normal function to refer to the internal table area in accordance with an interruption for advancing to processing to the interruption and a busy response function to perform a busy response to the host unit during the firmware active-interchange, and a second interruption control section serving, as an interruption handling function, only a busy response function to accomplish a busy response to the host unit during the firmware active-interchange.

Abstract: A field insulating film defines a plurality of active regions disposed regularly in terms of two dimension on the surface of a semiconductor substrate. Each active region includes one bit contact region and subsidiary active regions extending from the bit contact region in four directions. A plurality of first word lines are formed which extend as a whole in a first direction on the semiconductor substrate, and a plurality of second word lines are formed which extend as a whole in a second direction on the semiconductor substrate, crossing the first word lines. Two subsidiary active regions cross the first word lines and remaining two subsidiary active regions cross the second word lines. A plurality of bit lines are formed which extend as a whole in the first and second directions on the semiconductor substrate, crossing each other. Each bit contact region is connected to a corresponding one of the bit lines. Four transistors share one bit contact, and these four transistors have different word lines.

Abstract: A non-volatile semiconductor memory cell array including an MOS transistor having a vertical channel along an inside wall of a trench in each cell is developed for high density integration and high speed operations. One aspect of the invention is that the trench is formed such that the first trench having an aperture is formed slightly deeper than a drain diffusion layer on a semiconductor surface whereas the second trench having a smaller aperture than that of the first trench is formed in a center of a bottom of the first trench extending depthwise to the buried source diffusion layer such that the peripheral width of an aperture section of the first trench in the drain area is larger than that of the second trench in the source area.

Abstract: The invention provides a virus extermination method by which an error in operation by a user is prevented and optimum virus extermination based on a type of a virus can be performed without imposing much burden in operation.

Abstract: A transfer method of a push-button signal includes the steps of detecting a push-button signal created by an end user terminal during a state in which the end user terminal is connected to a remote service system by an exchange via a network, by using a push-button signal receiver, encoding the push-button signal detected by the push-button signal receiver to a produce a push-button transfer signal by using the push-button signal receiver, and transmitting the push-button transfer signal to the service system from the exchange to the service system via a signal line of the network.

Abstract: The semiconductor device includes a substrate, a semiconductor component, and a cap covering the semiconductor component and attached to the substrate. The cap has a top wall, a plurality of side walls 14 extending downward from the top wall and a bottom wall. Opening are provided in the side walls of the cap at corners thereof. Due to the provision of openings, the cap can be manufactured without deformation thereof. Air or liquid can flow into, or out of, the interior of the cap, after the semiconductor deviced is completed.

Abstract: A high temperature oxide superconductor is efficiently protected from the affects of water and acids by forming a passivation layer of a fluoride. The fluoride layer comprises a fluoride composed of one or more elements composing the oxide superconductor and/or one or more elements that can compose an oxide superconductor by replacing at least in part one or more elements composing the oxide superconductor.

Abstract: A finite impulse response circuit includes a delay line having a plurality of taps, receiving an input signal, a multiplying part for multiplying coefficients to signals obtained from the taps and adding multiplied results, and a shaping part for shaping the input signal by adjusting the coefficients. The shaping part includes a first tap coefficient setting circuit for correcting a signal distortion which is asymmetrical to right and left with respect to a signal point, and a second tap coefficient setting circuit for correcting a signal distortion which is symmetrical to the right and left with respect to the signal point. The first tap coefficient setting circuit sets the coefficient independently of the second tap coefficient setting circuit.

Abstract: A semiconductor device formed on an epitaxial substrate includes a high-resistance region in the vicinity of an interface between a doped semiconductor substrate and an epitaxial layer thereon. The high-resistance region is advantageously formed by an ion implantation process of a dopant opposite to a dopant contained in the doped semiconductor substrate such that there is formed a depletion of carriers in the vicinity of the foregoing interface.

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core.

Abstract: An exchange constituting an ATM network administers the number of UBR connections for every line port included in the exchange. Upon receiving a request for setting a UBR connection, the exchange determines the route of the UBR connection on the basis of the number of the UBR connections administered for every line port included in the exchange.

Abstract: A high speed address sequencer allows for a generation of address signals using a clock with higher frequency. The high speed address sequencer can be used in many semiconductor devices, especially in flash memory devices. By reducing a number of gate delays, the high speed address sequencer can generate all address signals in a reduced time period. By using an address signal as a clock for generation of some of the other address signals, the high speed address sequencer is allowed more time to generate all address signals with a given clock frequency. The reduction in the number of gate delays can be combined with the use of the address signal as a clock.

Abstract: One aspect of the present invention is characterized in that an input buffer circuit constitutes either 2 sets, or a plurality of sets relative to 1 input signal, either a pair of complementary internal clocks, or a plurality of internal clocks are generated by frequency-dividing a supplied clock inside the integrated circuit device, and input signals are received and latched either in synchronization with a pair of complementary clocks, or in synchronization with a plurality of clocks in accordance with an input buffer of either 2 sets or a plurality of sets. The output of input buffers of either 2 sets or a plurality of sets are combined by a combining circuit, and supplied internally. An H level or an L level period is set for the internally-generated internal clock so that outputs from the various input buffers are not in contention with one another.

Abstract: A self-timing control circuit relating to the present invention comprises a clock cycle counting circuit for counting ocillation pulses during a period corresponding to a cycle of the master clock and generating a clock cycle count value. The count value for a period corresponding to the cycle of the master clock is calculated with this clock cycle counting circuit. The self-timing control circuit further comprises a control clock generating portion for generating the control clock, as timed by synchronizing with the master clock, starting a count of the oscillation pulses, and counting up to the clock cycle count value. As a result, the control clock generated is delayed from the master clock by the time taken to count to the measured count value. The timing of the control clock is delayed from the master clock by one cycle or an integer multiple thereof.