Patents Assigned to Fujitsu
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Patent number: 6256334Abstract: A base station apparatus for a radiocommunication network in which radiocommunication with one or more radio terminal apparatuses is established according to a frequency hopping scheme. The base station apparatus includes a search section which searches for another radiocommunication network in the vicinity of the base station apparatus when the base station apparatus is started, and when another radiocommunication network is detected, obtains the pattern and time of frequency hopping in another radiocommunication network. A frequency hopping selection/setting section selects the pattern obtained by the search section as the frequency hopping pattern for the base station apparatus, and selects, on the basis of the time obtained by the search section, timing at which the frequency hopping based on the pattern does not cause frequency interference with respect to frequency hopping performed in another radiocommunication network, and carries out frequency hopping of the pattern at the thus-selected timing.Type: GrantFiled: September 22, 1997Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventor: Hideo Adachi
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Patent number: 6256316Abstract: In a centralized supervisory system having a plurality of individual supervisory devices which assembles control signal cells and main signal cells into frames and send the frames, and a centralized supervisory device which collects the supervisory information included in the control signal cells from the individual supervisory devices and sends the main signal cells to a network, maximum bands for control signals are determined, for the respective individual supervisory devices, on the basis of lengths of respective data to be transmitted. In each of the individual supervisory devices, a given number of control signal cells are arranged in each frame so that the control signals are transmitted within the maximum band. Then, the frames are sent to the centralized supervisory device.Type: GrantFiled: July 8, 1998Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventor: Kojun Mitani
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Patent number: 6255916Abstract: An object of the present invention is to realize a resonator-type SAW filter permitting higher extra-passband suppressibility by minimizing occurrence of an unwanted spurious peak. A resonator-type SAW filter in which a plurality of SAW resonators each having reflectors and an interdigital transducer and being connected in series and parallel with the other, wherein in at least one of the SAW resonators, particularly in at least one of the SAW resonators connected in series with one another, an inter-electrode pitch &lgr;REF in the reflectors has a different value from an inter-electrode pitch &lgr;IDT in the interdigital transducers.Type: GrantFiled: February 7, 1996Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventors: Yoshitaka Nakamura, Sumio Yamada, Sen Minemura
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Publication number: 20010005298Abstract: A suspension has a head slider loading prearranged portion on which a head slider integrally having a head is loaded, a head IC chip mounting prearranged portion on which a head IC chip is mounted, and wiring patterns which extend from the head slider loading prearranged portion. The head slider is loaded and supported on the head slider loading prearranged portion of the suspension. The head IC chip is mounted on the head IC chip mounting prearranged portion of the suspension. The head IC chip mounting prearranged portion includes through holes formed in the suspension and head IC chip mounting terminals on a surface of the suspension, which surface is opposite to a surface on which the head slider loading prearranged portion is provided, the terminals being electrically connected with the extending ends of said wiring patterns via the through holes, the terminals being provided in an arrangement corresponding to terminals of the head IC chip.Type: ApplicationFiled: February 27, 2001Publication date: June 28, 2001Applicant: Fujitsu LimitedInventor: Shinji Hiraoka
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Publication number: 20010005676Abstract: A radio switching system includes a mobile subscriber; a base station controller for controlling a transmission and reception of a signal of the mobile subscriber within an own cell; a mobile switching center connecting with a plurality of the base station controllers; and a home location register for storing home zone information whether or not the mobile subscriber is a subscriber of home zone services. The mobile switching center judges whether or not a registration is accepted with respect to a location registration request inside/outside a home zone of the mobile subscriber, based on home zone information sent from the home location register.Type: ApplicationFiled: December 26, 2000Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventors: Hiroyo Masuda, Masaya Suzuki
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Publication number: 20010005160Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.Type: ApplicationFiled: December 22, 2000Publication date: June 28, 2001Applicant: Fujitsu LimitedInventor: Masao Taguchi
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Publication number: 20010005402Abstract: A distortion compensating apparatus for compensating for a distortion of a transmission power amplifier. A delay time decision unit calculates the correlation between a transmission signal and a feedback signal fed back from the output side of the transmission power amplifier while varying phase difference between both signals, and decides the total delay time caused in the transmission power amplifier and a feedback loop on the basis of the phase difference in which the correlation is the maximum. A delay unit delays the transmission signal before a distortion compensation processing by the total delay time, and inputs the delayed signal into a distortion compensating apparatus arithmetic unit, which calculates and stores a distortion compensation coefficient on the basis of the transmission signal and the feedback signal fed back from the output side of the transmission power amplifier.Type: ApplicationFiled: December 22, 2000Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventors: Kazuo Nagatani, Tokuro Kubo, Takayoshi Ode, Yasuyuki Oishi
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Publication number: 20010005297Abstract: A non-magnetic gap layer is formed on a lower magnetic core layer. A magnetic layer for an upper magnetic pole piece as well as a non-magnetic cap layer is sequentially formed on the non-magnetic gap layer. A lower magnetic pole piece is shaped out of the lower magnetic core layer by employing the upper magnetic pole piece as a mask. A non-magnetic insulating layer is then formed all over the surface of the lower magnetic core layer. The non-magnetic cap layer is completely covered with the non-magnetic insulating layer. The non-magnetic insulating layer is then subjected to a flattening polishing process until the non-magnetic cap layer is exposed. The exposed non-magnetic cap layer is removed to expose the upper magnetic pole piece. The upper magnetic pole piece suffers from no abrasion in the flattening polishing process, so that the thickness of a narrower auxiliary upper magnetic pole can be set at a predetermined thickness at a higher accuracy.Type: ApplicationFiled: January 17, 2001Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventor: Yoshinori Otsuka
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Publication number: 20010005822Abstract: A noise suppression apparatus is realized by at least one linear prediction analyzing circuit. Each linear prediction analyzing circuit includes: an adaptive filter which produces a linear prediction signal based on a first speech signal on which noise is superimposed, and outputs the linear prediction signal as a second speech signal in which the noise is suppressed; a subtraction unit which obtains a difference between the linear prediction signal and the first speech signal, and outputs the difference as a prediction error; and a coefficient updating unit which updates coefficients of the adaptive filter based on the first speech signal and the prediction error so as to minimize the prediction error. The noise suppression apparatus may includes a cascade connection of a plurality of linear prediction analyzing circuits each having the above construction.Type: ApplicationFiled: December 13, 2000Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventors: Kensaku Fujii, Juro Ohga, Tsutoma Hoshino, Junichi Sakaguchi, Toshio Kora
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Publication number: 20010005398Abstract: A decoded picture and parameters of a sequence layer, a GOP layer and a picture layer respectively for displaying the decoded picture are stored as a set in each of picture banks and parameter banks of a frame memory. Parameters of each layer stored as a set with a picture decoded immediately before are read out. Parameters attached to a picture to be decoded are decoded overwritten. Thus, the parameters of each layer stored as a set with the picture to be decoded are generated.Type: ApplicationFiled: December 27, 2000Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventors: Tadayoshi Kono, Mitsuhiko Ohta
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Publication number: 20010005405Abstract: “100”, which is one of the (1, 7) RLL codes, is used as a clock acquisition pattern. After temporarily judging the sample output to be one of (1, −1), the phase error computing result for three samples (symbols) is added so as to cancel the errors of phase computing. Therefore the number of judgment states can be decreased, and phase can be acquired at high-speed even if the amplitude at acquisition has not been defined. At tracking, the sample output is judged to be one of three groups, [1+a, 1], 0, and [−1, −1−a]. Using the state transition of (1, 7) RLL codes, [1+a, 1] and [−1, −1−a] are distinguished. Since the number of judgment states decreases, judgment accuracy improves.Type: ApplicationFiled: February 26, 2001Publication date: June 28, 2001Applicant: FUJITSU LIMITEDInventor: Kaneyasu Shimoda
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Publication number: 20010005037Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.Type: ApplicationFiled: February 2, 2001Publication date: June 28, 2001Applicant: Fujitsu LimitedInventor: Katsumi Kakamu
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Publication number: 20010005157Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.Type: ApplicationFiled: February 12, 2001Publication date: June 28, 2001Applicant: Fujitsu LimitedInventors: Masao Taguchi, Hiroyoshi Tomita, Yasurou Matsuzaki
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Publication number: 20010005033Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.Type: ApplicationFiled: December 27, 2000Publication date: June 28, 2001Applicant: Fujitsu LimitedInventor: Shunji Nakamura
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Patent number: 6252458Abstract: A differential amplifier having an integrated resistance load type differential pair in which a constant current which varies to suppress a small signal gain variation of a resistance load type differential pair caused by variations of circumferential conditions and manufacturing process conditions and a constant current which varies to suppress a limiter amplitude variation of the resistance load type differential pair caused by the variations of the same conditions are mixed at a fixed ratio under a condition which is most frequently used among the circumferential conditions and a condition which is best achieved among the manufacturing process conditions, which is used as a bias current of the differential pair.Type: GrantFiled: October 28, 1999Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventor: Kohei Shibata
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Patent number: 6251721Abstract: After an SAC film is formed to a thickness not to fill the spaces between gate electrodes in a memory cell region, a silicon oxide film is formed to a thickness to fill the spaces. A side wall made of a silicon oxide film is formed on the side surface of only a gate electrode in a peripheral circuit region, and a metal silicide is formed on the exposed substrate surface. A BLC film is formed on the entire surface. A contact hole is formed in self alignment using the SAC film and the BLC film. In this method, silicidation of the source/drain of a transistor in the peripheral circuit region and the self-alignment technique such as BLC or SAC can be simultaneously used to enable an increase in the degree of integration and improvement of performance of a semiconductor device having a metal silicide on the transistor in the logic circuit.Type: GrantFiled: April 7, 2000Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventors: Kenichi Kanazawa, Koichi Hashimoto, Yoshihiro Takao, Masaki Katsube
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Patent number: 6252269Abstract: According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.Type: GrantFiled: October 25, 1999Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventors: Masatomo Hasegawa, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Toru Koga, Yuki Ishii
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Patent number: 6251016Abstract: A lottery on a network like the Internet can be more easily attained by preventing impersonation and validating participation. In a preferred embodiment, the opportunity to participate in the lottery is a reward for viewing an advertisement. When the advertisement is viewed a lottery ticket issuing number is displayed as an image file on the browser of the user viewing the advertisement. The image file is sent from the server providing the lottery service to the browser with HTML source to display the number. The image file on the lottery server is deleted after being sent, so that if the user requests re-display of the ticket issuing number display, the number cannot be obtained. The lottery server maintains a database of date and time stamped. requests for lottery ticket issuing numbers to prevent multiple requests during a single session. The user is requested to input the number displayed by the browser to find out whether it is a winning number.Type: GrantFiled: October 31, 1997Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventors: Kazuaki Tsuda, Hiroyuki Abe, Izumi Muraki, Seiji Yoshizawa, Akitoshi Kaneko
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Patent number: 6252826Abstract: Oscillating precision of the first and the second oscillating sections each having the same oscillation frequency is determined in the oscillating precision determining section according to the timing of a signal supplied from the external time source, and in the internal time stepping control section, stepping control is provided over the internal time using a reference clock oscillated by any of the first and the second oscillating sections according to a result of determination of the oscillation precision.Type: GrantFiled: August 27, 1998Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventors: Tetsuya Kaizu, Michio Kai
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Patent number: 6252687Abstract: The invention provides an optical wavelength multiplex transmission method wherein a band in the proximity of a zero dispersion wavelength of an optical fiber is used and optical signals are disposed at efficient channel spacings taking an influence of the band, the wavelength dispersion and the four wave mixing into consideration to realize an optical communication system of an increased capacity which is not influenced by crosstalk by FWM. When optical signals of a plurality of channels having different wavelengths are to be multiplexed and transmitted using an optical fiber, a four wave mixing suppressing guard band of a predetermined bandwidth including the zero-dispersion wavelength &lgr;0 of the optical fiber is set, and signal light waves of the plurality of channels to be multiplexed are arranged on one of the shorter wavelength side and the longer wavelength side outside the guard band.Type: GrantFiled: April 27, 1998Date of Patent: June 26, 2001Assignee: Fujitsu LimitedInventors: George Ishikawa, Hideyuki Miyata, Hiroshi Onaka, Motoyoshi Sekiya, Kazue Otsuka