Patents Assigned to Fujitsu
  • Patent number: 6184476
    Abstract: A thin multi-layer circuit board having alternately stacked wiring pattern layers, including a top wiring pattern layer and insulating layers on an insulating plate-like substrate. The wiring pattern layers are electronically connected through vias in the insulating layers to form a predetermined circuit pattern by said wiring pattern layers. A metallic barrier layer is formed on the top wiring pattern layer, except at an exclusion zone of the metallic barrier layer. An electronic part-mounting pad layer and a remodeling pad layer are formed on the metallic barrier layer. The remodeling pad layer is arranged adjacent the electronic part-mounting pad layer, with the exclusion zone therebetween.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Ltd.
    Inventors: Yasuhito Takahashi, Yasunaga Kurokawa, Kenji Iida, Masaru Sumi, Yuichiro Ohta, Toshiro Katsube, Kazuo Nakano, Norikazu Ozaki, Hiroyuki Katayama
  • Patent number: 6183283
    Abstract: An electrical contact element for a connector, including a first contact end, a second contact end opposed to the first contact end, and an intermediate section integrally joining the first and second contact ends with each other. The intermediate section is provided integrally with a first projection tightly press-fitted into an electro-insulating body of the connector, and with a second projection abutted onto a surface of the connector body to permit the contact element to be fixedly supported in the connector body against an angular displacement of the contact element about the first projection. The electro-insulating body of the connector includes a base for supporting the plural electrical contact elements in a mutually isolated mariner, and a pair of columns extending in the same direction from longitudinally opposed ends of the base.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Takamisawa Component Limited
    Inventors: Fumio Kurotori, Osamu Daikuhara, Kazuyuki Futaki
  • Patent number: 6185022
    Abstract: To improve the OSNR on a receiving side it is necessary to control pre-emphasis, and further to automatically control the pre-emphasis. Furthermore, when carrying out wavelength-division multiplexing, it is also necessary to control wavelength. The optical spectrum of signal lights is detected in both a transmitting terminal station and a receiving terminal station, a transmitting side spectrum detection result and a receiving side spectrum detection result are compared, and the levels and wavelengths of signal lights to be transmitted are controlled.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Shin-ichirou Harasawa
  • Patent number: 6185103
    Abstract: A removable, EMI-shielding hard disk drive module for a notebook computer is pivotally insertable into the computer through an opening in the computer's base plate. Connectors fixedly mounted on the module and computer, respectively, mate when the module is fully inserted. A pin on the module cooperates with a movable cam on the computer to automatically lock the module in position when it is fully inserted, and to positively but smoothly disengage the connectors when the lock is released for removal of the module. To facilitate removal, the cam may lightly hold the module, after the connectors are disengaged, in a position where the module is easy to grasp and remove.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Kevin Seichi Yamada
  • Patent number: 6185186
    Abstract: The invention relates to a fixed-length cell handling switching system and a method for controlling a read rate of a fixed-length cell. The fixed-length cell handling switching system has a quality class identifier relating unit for relating a quality class identifier according to a quality class of a cell, a quality controlling buffer unit including a managing unit, a buffer and a read rate information holding unit, and a call handling control unit including a virtual band setting unit for setting a virtual band of the buffer and a read rate setting control unit for setting and controlling a read rate, wherein a read rate for each quality class is dynamically changed, whereby a transmitting process is conducted according to a required quality class without affecting fixed-length cells of calls having different qualities on each other.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Watanabe
  • Patent number: 6184646
    Abstract: A stepping motor control unit for controlling a stepping motor is provided with a time measuring section for measuring time outputting a time completion pulse when a predetermined time elapses, a mutual excitation waveform output circuit switching a mutual excitation waveform to be applied to the stepping motor in response to the time completion pulse, an interrupt prohibit circuit outputting an interrupt enable signal which indicates an interrupt enable state or an interrupt prohibit state, an interrupt generating circuit generating an interrupt signal in response to the time completion pulse only when the interrupt enable signal indicates the interrupt enable state, and a processor controlling the stepping motor every time the interrupt signal is received.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Teruaki Yagoshi, Takakazu Kobayashi
  • Patent number: 6185647
    Abstract: A priority decision circuit decides priorities of a plurality of slots on the basis of access frequencies or the like. In conformity with these priorities, a bus mapping circuit performs mapping allowing a slot having a higher priority to be connected to the upper hierarchical bus whereas it performs mapping allowing a slot having a lower priority to be connected to the lower hierarchical bus.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Keiko Shibuya
  • Patent number: 6185308
    Abstract: A key recovery information distribution device is provided between a recoverer device and a key recovery device, recovers a data key for the recoverer device, and reduces the load of the recoverer device. Data is encrypted using the data key and stored with key recovery information. The recoverer device which decrypts the encrypted data distributes the key recovery information to key recovery devices through the key recovery information distribution device to recover key information. A recoverer is authenticated directly between the key recovery device and the recoverer device, and then the key information is transmitted to the recoverer device, and the recoverer device recovers the data key.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: February 6, 2001
    Assignees: Fujitsu Limited, NEC Corporation, Hitachi, Ltd.
    Inventors: Hiroyuki Ando, Ichir{overscore (o)}u M{overscore (o)}rita, Yasutsugu Kuroda, Naoya Torii, Masashi Yamazaki, Hiroshi Miyauchi, Kazue Sako, Seiichi Domyo, Hiroyoshi Tsuchiya, Seiko Kanno
  • Patent number: 6183881
    Abstract: A magnetic thin film forming method forms a magnetic thin film on a conductive film by electroplating using a plating bath containing Ni ions, Fe ions, Mo ions and an organic acid. A concentration of the organic acid in the plating bath is 3-20 times a concentration of the Mo ions in the plating bath. An organic acid concentration in the plating bath versus an Mo ion concentration of the plating bath is set to be a suitable value, whereby an Mo mixed amount in the magnetic thin film can be set to be a suitable value. Accordingly, a magnetic thin film having a large specific resistance value and good magnetic characteristics can be formed.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Sanae Shimizu
  • Patent number: 6183302
    Abstract: A plug connector includes an electrically insulating body including a housing and a pair of arms; a plurality of pairs of first and second right-angled signal contact elements supported by the housing such that the first right-angled signal contact element is arranged above the second right-angled signal contact element, each of the right-angled signal contact elements having a substantially right-angled contact portion protruding backward from the housing and a leading portion inserted into the housing, the contact portion having a horizontal part and a vertical part; a plurality of ground contact elements supported by the housing and disposed alternately with the plurality of pairs of first and second right-angled plug signal contacts, each of the ground contact elements provided with two ground terminals; and upper and lower electrically insulating brackets assembled to the housing.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Takamisawa Component Limited
    Inventors: Osamu Daikuhara, Junichi Akama
  • Patent number: 6185256
    Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Junji Ogawa
  • Patent number: 6185071
    Abstract: A magnetic head slider having an air inlet end an an air outlet end, and includes a pair of rails formed on a disk opposing surface opposed to a magnetic disk, each of the rails having a flat air bearing surface for generating a flying force during rotation of the disk, and an electromagnetic transducer formed on one of the rails in the vicinity of the air outlet end. The magnetic head slider further includes a plurality of streamlined pads formed on the air bearing surfaces of the rails in the vicinity of the air inlet end and in the vicinity of the air outlet end.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Yoshimichi Asanai, Masaharu Sugimoto
  • Patent number: 6184643
    Abstract: An apparatus is automatically conveying cartridges reliably and correctly without causing errors, making it possible to enhance the operation efficiency and performance of the apparatus. The apparatus is automatically conveying cartridges disposed adjacent to a recording/reproducing apparatus, and is comprised of a cell mechanism having racks, an accessor mechanism having an accessor, and a conveyance control unit for controlling the conveyance of the cartridges by controlling the accessor mechanism, wherein the accessor is provided with catcher hands, a catcher hand drive mechanism, an open detector mechanism for detecting the open state of said catcher hands, and a closed detector mechanism for detecting the closed state of said catcher hand.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Hitomi Akiyama, Yoshiki Akiyama
  • Patent number: 6184669
    Abstract: There is disclosed a current control circuit, disposed between a primary terminal and a secondary terminal, for controlling a current flowing from the primary terminal to the secondary terminal. An overcurrent flowing through a resistance R1 is detected by a PNP transistor. A maximum value of a current flowing through a MOSFET is determined by a voltage dropped by a voltage drop correspondence by a diode from a voltage of the collector of the PNP transistor.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventor: Kouichi Matsuo
  • Patent number: 6184475
    Abstract: A lead-free solder alloy composition contains Sn, Bi and In, with respective contents such that the solder alloy composition provides a liquidus temperature below the heat resistant temperature of a work to be soldered. The alloy contains not more than about 60 wt % Bi; not more than about 50 wt % In; optionally at least one element selected from Ag, Zn, Ge, Ga, Sb, and P; and Sn. Also, lead-free solder powders containing same, and printed circuit boards, electronic components and electronic apparati employing such alloy.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Masayuki Kitajima, Masakazu Takesue, Yasuo Moriya, Yoshinori Nemoto, Yumiko Fukushima
  • Patent number: 6185517
    Abstract: An electromagnetic field intensity computing apparatus for computing electromagnetic field intensity of an electric circuit device in a moment method obtains according to the electric current distribution an electric current of a ground layer and models a transmission line, ground layer, dielectric portion, etc. to be analyzed. When a plate to be analyzed is divided into a plurality of patches, the regularity in given structure data is automatically extracted to compute the mutual impedance among a portion of patches and apply the computation result to other portions. When elements to be analyzed meet the conditions that the electric length of the elements is short and the elements are distant from each other, the mutual impedance can be computed in an approximation obtained under various conditions. Furthermore, approximating a portion near a pigtail portion of a coaxial cable using a polygon allows a vertical electric current to be properly connected to each unit.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Shinichi Ohtsu, Makoto Mukai
  • Patent number: 6185162
    Abstract: A magneto-optical memory device includes a first unit projecting a light beam onto a desired position on a recording medium, and a second unit applying a magnetic field to a position onto which the light beam is projected. The second unit applies, to the recording medium, a predetermined magnetic field within a magnetic field intensity range wherein a rate of change of a reproduced signal amplitude at the time of reproduction with respect to a magnetic field intensity becomes large. The relative positions of the second unit and the first unit are adjusted in accordance with a reproduced signal amplitude thus obtained.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Yasukiyo Kunimatsu, Kazuhito Yokoyama
  • Patent number: 6184947
    Abstract: A thin film transistor matrix including: a plurality of thin film transistors disposed in a matrix shape on a transparent insulating substrate, each thin film transistor having a gate electrode, a source electrode and a drain electrode; a pixel electrode formed on the transparent insulating substrate and connected to the source electrode of each of the plurality of thin film transistors; a plurality of gate bus lines connected to the gate electrode, disposed as a whole along a row direction on the transparent insulating substrate, and including a first lamination of a first metal layer and an underlying first semiconductor layer; and a plurality of drain bus lines connected to the drain electrode, disposed as a whole along a column direction on the transparent insulating substrate, and including a second lamination of a second metal layer and an underlying second semiconductor layer.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Kiyoshi Ozaki, Makoto Igarashi
  • Patent number: D437399
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: February 6, 2001
    Assignee: Fujitsu General Limited
    Inventor: Katsuya Nonaka
  • Patent number: D437468
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: February 6, 2001
    Assignee: Fujitsu Limited
    Inventors: Katsuyuki Fukutake, Taku Ando, Takayuki Kakizaki, Hiroyuki Moto, Henry Young Chin, Chin Hor Lee