Patents Assigned to Fujitsu
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Patent number: 6188738Abstract: Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.Type: GrantFiled: March 13, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Hisaya Sakamoto, Akihiko Sugata, Akimitsu Miyazaki, Tetsuya Kiyonaga
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Patent number: 6187652Abstract: A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.Type: GrantFiled: September 14, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: William T. Chou, Solomon I. Beilin, Michael Guang-Tzong Lee, Michael G. Peters, Wen-Chou Vincent Wang
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Patent number: 6187600Abstract: A surface layer portion of a silicon substrate is etched by using a mixed solution which contains ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a weight ratio of 1:(1.3 to 2.65):(275 to 433). The density of the etch pits which have occurred in a surface of the silicon substrate whose surface layer portion was etched by the etching step is measured. The crystal quality, etc. of the silicon substrate are evaluated before a process for manufacturing semiconductor devices using such silicon substrates, in order to avoid a lowering of the yields of the semiconductor devices.Type: GrantFiled: October 20, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Yoichi Fujisawa, Kaoru Ogawa, Kenichi Hikazutani
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Patent number: 6186722Abstract: An apparatus suitable for producing semiconductors. The apparatus includes a processing chamber, a first preparatory chamber, and a second preparatory chamber. Workpieces are transferred to the processing chamber for processing in a vacuum. The first and second preparatory chambers are used for transferring the workpiece between the processing chamber and an exterior exposed to atmospheric pressure without exposing the processing chamber to the atmospheric pressure. The first and second preparatory chambers are aligned vertically, which reduces the floor space occupied by the apparatus.Type: GrantFiled: February 24, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventor: Hidenobu Shirai
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Patent number: 6188640Abstract: A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the output timing of a data signal. An output buffer receives the output control signal and then outputs the data signal in accordance with an output internal clock signal. The phase of the output internal clock signal is advanced from that of the input internal clock signal. The output control circuit also includes a latency counter that generates the output control signal by counting the cycles of a second output internal clock signal, which is delayed from the first output internal clock signal.Type: GrantFiled: September 17, 1999Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Tadao Aikawa, Yasuharu Sato, Hiroyuki Kobayashi, Waichirou Fujieda
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Patent number: 6188533Abstract: Desired data recorded in a recording medium is read as a result of a head scanning a desired track, track tracking information for detecting the amount of displacement of said head with respect to the track and address information for identifying the recorded data are also recorded in said recording medium, and the track tracking information and the address information are used so that the head scans the desired track properly. The recording medium is used in which recording medium the track tracking information and the address information is disposed so that the head first scans the track tracking information and then scans the address information. Whether the track, which the head scans, is the desired track is determined from the address information. The amount of displacement of the head with respect to the track is detected from the track tracking information. The desired data is read from the desired track.Type: GrantFiled: March 27, 1998Date of Patent: February 13, 2001Assignee: Fujitsu Ltd.Inventor: Osamu Yoshida
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Patent number: 6188090Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.Type: GrantFiled: February 20, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Shinji Miyagaki, Takashi Eshita, Satoshi Ohkubo, Kazuaki Takai
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Patent number: 6189014Abstract: A method of managing files of an interchangeable storage medium having a RAM area defining an independent RAM section and a ROM area defining an independent ROM section, each section having a file management area for storing file management data and a file area for storing files. The method includes reading file management information out of a file management area of the ROM section in response to a request for establishing a section in which the RAM area and the ROM area are mixed, converting the file management information of the ROM section to file management information of the mixed RAM-ROM section, writing the file management information of the mixed RAM-ROM section in a file management area of the mixed section, and managing ROM files and RAM files as files of the mixed section.Type: GrantFiled: June 28, 1996Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventors: Kazuo Nakashima, Kenichi Utsumi
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Patent number: 6187640Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below tType: GrantFiled: November 17, 1998Date of Patent: February 13, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
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Patent number: 6189144Abstract: An object program is produced in a data processing system by linking a plurality of program modules. Internal program modules, which have been produced by means of a high-level language translator, and external program modules, are provided with names from mutually exclusive name classes. A matching routine of a first type is produced for each of the internal program modules, and a matching routine of a second type is produced for each of the program modules that are called by the internal program modules. The matching routines bridge different linking declarations.Type: GrantFiled: December 17, 1999Date of Patent: February 13, 2001Assignee: Fujitsu Siemens Computers GmbHInventor: Christian Weber
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Patent number: 6188686Abstract: Switching apparatus, for use in an ATM network for example, which includes a plurality of data units; cross-connect switching units, having a plurality of input ports and output ports, for providing data transfer paths, each path serving to pass data received at one of the input ports to one of the output port; and connection units connected to the input ports and to the data units, for delivering data from designated source data units to respective input ports and for delivering the data, after passage through one of the data transfer paths, from the output ports to respective designated destination data units. Two data units, which together constitute a data delivery group associated with an input port, are connected to each connection unit and the connection unit serves to deliver data from the two different data units of the data delivery group, at different respective times, to that associated input port. In such apparatus the number of input ports of the switching units is reduced.Type: GrantFiled: June 5, 1997Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventor: Graeme Roy Smith
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Patent number: 6188573Abstract: An information processing device includes a main body having a bay, and a peripheral device which can detachably be loaded to the bay. The peripheral device includes a cooling unit, which is accommodated in the bay with the peripheral device loaded to the bay.Type: GrantFiled: September 25, 1998Date of Patent: February 13, 2001Assignee: Fujitsu LimitedInventor: Kenji Urita
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Patent number: 6185166Abstract: An optical information recording/reproducing apparatus records information on and/or reproduces information from an optical recording medium based on a reflected light beam from the optical recording medium. The apparatus includes a light splitting part having a plurality of light splitting stages which split the reflected light beam from the optical recording medium into a plurality of light beams, and a photodetector unit including a plurality of photodetectors which receive the plurality of light beams from the light splitting part. The photodetector unit includes a plurality of photodetectors which receive light beams used to detect a focal error, at least one photodetector which receives a light beam used to detect a tracking error, and a plurality of photodetectors which receive light beams used to detect magneto-optic information recorded on the optical recording medium.Type: GrantFiled: December 18, 1997Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Koichi Tezuka, Kyoko Miyabe, Satoshi Itami, Tohru Fujimaki, Kazushi Uno
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Patent number: 6185201Abstract: The present invention is directed to a multiplex radio transmission/receiving system. The system includes a plurality of transmission sections provided so as to correspond to a plurality of channels, and a plurality of receiving sections provided so as to correspond to the plurality of channels. Each transmission section includes a modulation section, a first frequency conversion section, a first band-pass filter, a second frequency conversion section, and a second band-pass filter. Each receiving section includes a third band-pass filter, a third frequency conversion section, a fourth band-pass filter, a fourth frequency conversion section, and a demodulation section. By selection of an optimum value for a second intermediate frequency of a transmitter and for a third intermediate frequency of a receiver, a group of transmission radio frequencies (RF) signals and a group of local frequency signals are allocated without overlap.Type: GrantFiled: November 6, 1998Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Hiroyuki Kiyanagi, Toshiaki Suzuki, Yasuhiro Shibuya, Hiroshi Suzuki
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Patent number: 6185149Abstract: A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.Type: GrantFiled: June 28, 1999Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Masao Taguchi, Yasuharu Sato, Takaaki Suzuki, Tadao Aikawa, Yasurou Matsuzaki, Toshiya Uchida
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Patent number: 6185040Abstract: A virtually imaged phased array (VIPA) which receives an input light at a respective wavelength, and produces a spatially distinguishable output light in accordance with the wavelength of the input light. The VIPA has first and second surfaces. The second surface has a reflectivity which causes a portion of light incident thereon to be transmitted therethrough. The first and second surfaces are positioned so that the input light is reflected a plurality of times between the first and second surfaces to cause a plurality of lights to be transmitted through the second surface. The plurality of transmitted lights interfere with each other to produce an output light which is spatially distinguishable from an output light produced for an input light having any other wavelength within the continuous range of wavelengths. A spacer element has an approximately zero thermal expansion coefficient and maintains the relative positioning between the first and second surfaces to be constant.Type: GrantFiled: July 7, 1999Date of Patent: February 6, 2001Assignees: Fujitsu Limited, Avanex CorporationInventors: Masataka Shirasaki, Simon Cao
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Patent number: 6184133Abstract: A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.Type: GrantFiled: February 18, 2000Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Makoto Iijima, Tetsushi Wakabayashi, Toshio Hamano, Masaharu Minamizawa, Masashi Takenaka, Taturou Yamashita, Masataka Mizukoshi
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Patent number: 6184148Abstract: An interconnection pattern made of aluminum alloy, such as Al-Cu, on a semiconductor IC, is dry etched in an etching gas containing a chlorine component. Residual chlorine components on the substrate are difficult to remove, thus causing corrosion problems with respect to the patterned aluminum alloy layer. Accordingly, to prevent such corrosion, a photo resist stripping process is carried out at a location down stream of the etching process using a conventional stripping gas, such as CF4+O2, at room temperature. Next, and before the resist-stripped substrate is exposed to open air, the substrate is heated in a vacuum to a temperature above 100° C., to thus remove residual chlorine components. In an alternative method, the heating process is carried out concurrently with the resist stripping process.Type: GrantFiled: April 18, 1997Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventor: Moritaka Nakamura
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Patent number: 6185137Abstract: A memory device, such as a DRAM, includes multiple cell blocks, each having bit lines and word lines. Block control circuits are connected to respective ones of the cell blocks. The block control circuits supply a precharge signals to their associated cell blocks. A block control circuit which is connected to a defective cell block generates a precharge signal having a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block. The block control circuit sets the precharge signal to the precharge level when the defective cell block is activated and to the reset level when it is deactivated.Type: GrantFiled: December 9, 1999Date of Patent: February 6, 2001Assignee: Fujitsu LimitedInventors: Hajime Sato, Satoru Kawamoto
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Patent number: D437608Type: GrantFiled: June 26, 2000Date of Patent: February 13, 2001Assignee: Fujitsu General LimitedInventors: Yoshihiro Shiota, Yoichi Yamazaki