Patents Assigned to Fujitsu
  • Patent number: 6147783
    Abstract: An optical transmission system containing a protection system and a plurality of working systems. When a trouble occurs in the protection system to which one of the working system is switched, a line alarm indication signal (LINE AIS), which can be detected in a reception portion of a piece of terminal equipment, and can activate a switch control circuit, is transmitted to a piece of terminal equipment on the reception side. In response to the receipt of the line alarm indication signal (LINE AIS), the piece of terminal equipment on the reception side transmits a far end receive failure signal (FERF) through an protection system optical transmission line (PTCT2) to a piece of protection system terminal equipment on the transmission side, and transmits a path alarm indication signal (PATH AIS) which does not activate the switch control circuit, through an optical transmission line in the same terminal station to the pieces of working system terminal equipment in the same terminal station on the reception side.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Fumihiro Ikawa
  • Patent number: 6145744
    Abstract: A method of the invention reads a bar code based on bar-code data obtained by scanning the bar code with light. The method includes the steps of a) obtaining bar-code data, b) obtaining a sum of bar-data widths with respect to a predetermined number of bar data provided in at least one of a preceding portion and a following portion of the bar-code data, c) repeating the steps a) and b) once to obtain another sum, and d) making a comparison of the sum with another sum. The methods further includes a step of accepting the bar-code data as valid data when a result of the comparison satisfies a predetermined condition.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Motohiko Itoh, Shinichi Satoh, Mitsuo Watanabe, Hiroaki Kawai, Isao Iwaguchi
  • Patent number: 6146329
    Abstract: There is provided an ultrasonic diagnostic apparatus in which ultrasonic waves are transmitted into the subject, the ultrasonic waves reflected within the subject are received to obtain received signals, and an image is produced in accordance with the received signals thus obtained, and particularly to an ultrasonic diagnostic apparatus having a function of guiding a puncture needle to be introduced into the subject. Of a scanning area formed with a number of scanning lines scanned by ultrasonic waves, within the subject, a first area including a part or a whole of a passage of a puncture needle is scanned with a scanning density higher than that of a second area, excepting the first area, of said scanning area. A sensor which measures the tip length of the puncture needle is used to set up the first area.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Kenichi Hayakawa
  • Patent number: 6147826
    Abstract: A writing unit writes a first sync byte pattern SB1 to the head of data and writes a second sync byte pattern SB2 to the end of the data (DATA+ECC). When the first sync byte pattern SB1 is not detected, the data is stored into a memory, and after that, a reading unit reads out the second sync byte pattern SB2 in the memory. When the second sync byte pattern SB2 is detected, the reading unit reads out the data of a predetermined length DL in which a position that is preceding to the detecting position by only a predetermined data length (DL) is set to the head position from the memory and demodulates.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Hashimura
  • Patent number: 6147765
    Abstract: A computer communicates with a printer. The computer has a printer communication controller for controlling one-way and two-way modes for printing. The printer has a printing controller for controlling the one-way and two-way modes. The computer sends a switching signal to the printer through a switching signal line, to switch the printer from the one-way mode to the two-way mode. The switching signal is a signal in response to which the printer can return a response to the computer through a reception channel even if the printer is offline. Upon receiving the switching signal, the printer returns a response to the computer and switches to a pseudo two-way mode that is a temporary online state. If the computer sends a printing start command thereafter to the printer, the printer switches from the pseudo two-way mode to the two-way mode. This arrangement easily switches the one-way and two-way modes from one to another.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Noboru Yoneda
  • Patent number: 6146241
    Abstract: Methods and apparatuses for evenly polishing the entire polishing surface of a sample are described. One polishing apparatus of the present invention comprises: a platen having an upper surface upon which the sample surface is to be polished; a sample holder disposed opposite to the platen's upper surface, at least one of the platen and the sample holder being rotated about a first axis to effect polishing; a positioning means for changing the distance between the sample holder and the platen in response to a control signal; and a controller providing said control signal to the positioning means to control the operation of the positioning means during a polishing cycle, wherein the controller causes the positioning means to change the distance intermittently during the polishing cycle.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Michael G. Lee, Solomon I. Beilin
  • Patent number: 6147740
    Abstract: A liquid crystal panel has a pair of substrates disposed almost parallel to each other. On each of the substrates, an electrode and an alignment film are formed. A liquid crystal layer having a negative dielectric anisotropy is sandwiched by the substrates. In the absence of voltage applied across the electrodes, the molecules of the liquid crystal layer align almost perpendicular to the substrates. In this liquid crystal layer, a dichroic dye, preferably a blue dichroic dye, is added to absorb the yellow component of an incident light. Instead of adding the dye into the liquid crystal layer, a color compensation layer containing the dye is formed on or adjacent to at least one of the substrates. The yellow component of an incident light to the liquid crystal panel is absorbed by the color compensation layer. As a result, the liquid crystal panel and the liquid crystal display using the panel do not show yellow coloring when the panel is observed from oblique directions.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Hidefumi Yoshida, Katsufumi Ohmuro
  • Patent number: 6145737
    Abstract: A check is fed to a storage mechanism through a check carrier path. The storage mechanism carries the check to a check carrier unit by an operation of a gate mechanism. The check carrier unit carries the check as far as a storage box with carrier rollers. The check is discharged from the check carrier unit and stored in the storage box. The storage box is provided outside a safe. The storage box is detachably provided and has a cylinder lock provided on the door thereof.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Masayuki Imai, Kenichi Nashirozawa, Kazuto Kitano, Naomi Hori
  • Patent number: 6147916
    Abstract: A semiconductor memory device, such as a DRAM, includes a memory cell array and pairs of bit lines connected to the memory cells in the array. A precharge circuit is connected the bit line pairs and selectively provides the bit line pairs with a reference power supply voltage when the memory cells are being accessed and a precharge voltage when the memory cells are not being accessed. A correction circuit adjusts the precharge voltage in accordance with a difference between the precharge voltage and the reference power supply voltage so that the precharge voltage becomes substantially equal to the reference power supply voltage. A retention mode determination circuit detects when the memory device is in a retention mode (powered down state) and prevents access to the memory cells at this time.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Kiyonori Ogura
  • Patent number: 6147972
    Abstract: In a cell exchange, cell diagnosis of continuity with respect to an individual part operating in a band width for a speed faster than a cell feeding speed is enabled by using cell test equipment with a low cell feeding speed. The method of cell diagnosis of continuity for this purpose comprises a step of setting a plurality of paths between a diagnosed unit to which the cell diagnosis of continuity is applied and the cell test equipment; a step of almost substantially concentrating cells sent from the cell test equipment through a plurality of paths at the diagnosed unit; and a step of returning cells concentrated at the diagnosed unit to the cell test equipment via one of a plurality of paths.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Kazuei Onishi, Masatoshi Takita
  • Patent number: 6147858
    Abstract: A keyboard to which the portable type information apparatus, such as an electronic notebook, a pen computer or a portable digital assistants/terminal equipment, can be directly and detachably connected and by which a large quantity of information can be quickly inputted. The keyboard is provided with a connector, to which a portable type information apparatus is directly and detachably connected, and a plurality of keys through which the apparatus can be operated. The keys are arranged in the keyboard main body, and the connector is arranged in the keyboard movable section. The keyboard movable section is connected to the keyboard main body while an angle formed between the keyboard movable section and the keyboard main body can be arbitrarily changed and the angular position can be held by itself. The keyboard is provided with an engaging section by which the keyboard is mechanically engaged and fixed to the information apparatus.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Takamisawa Components Company
    Inventor: Kimiyo Takahashi
  • Patent number: 6147905
    Abstract: A non-volatile semiconductor memory device includes memory cell blocks in which n sectors for erasing are defined where n is an integer equal to or greater than 1. Each of the memory cell blocks includes sense amplifiers, and an activation signal generating circuit activating an activation signal for generating the sense amplifiers. Data held in the sense amplifiers of the memory cell blocks are continuously output in accordance with a burst length. Sectors related to blocks corresponding to the burst length are sequentially subjected to an erase operation.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Junji Seino
  • Patent number: 6147923
    Abstract: An NMOS capacitor 13 and a PMOS capacitor 18 for pumping up are connected in series to an output line 12. In middle point voltage control circuit 20, a power supply line at VCC is connected via a PMOS transistor 21 to the anode of a reverse-flow preventing diode 22 and the node of voltage VM, the cathode of the diode 22 is connected via an NMOS transistor 23 to a ground line, and control signals *BIN and AIN are provided to the gate electrodes of the transistors 21 and 23, respectively, in response to an address transition detection signal AT. An end point voltage control circuit 30 is connected between the gate electrode of the NMOS transistor 23 and one end of the PMOS capacitor 18, and is equipped with inverters 31 and 32 connected in series. In an initial state, VM is at 0V and VE and VOUT is at VCC. Next the node of VM becomes a floating state and VE is lowered to 0V. Finally the node of VM is raised to VCC to boost VOUT from VCC up to VCC(2+.alpha.), where 0<.alpha.<1.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Akihiro Nakano
  • Patent number: 6147830
    Abstract: A magnetic tape unit with a magnetic head for reading and writing data from and onto a magnetic tape. The magnetic tape is kept in constant contact with the magnetic head, and a reel motor travels the magnetic tape kept in contact with the magnetic head. Adhesion of the magnetic tape to the magnetic head is prevented by slowly driving the reel motor to travel the magnetic tape at a speed lower than a normal traveling speed for a read/write operation of the magnetic head, during a rest period when the read/write operation of the magnetic head is not performed.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Masayoshi Kobayashi, Keisuke Hoshino, Masaru Ohshita, Akira Takano, Makoto Sasaki, Makoto Matsuda, Toshihiko Fujii
  • Patent number: 6147906
    Abstract: The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: November 14, 2000
    Assignees: Advanced Micro Devices, Inc., Fujitsu Ltd.
    Inventors: Colin S. Bill, Shigekazu Yamada
  • Patent number: 6146931
    Abstract: A semiconductor device includes an ohmic electrode and a Schottky electrode respectively carrying interconnection patterns with intervening adhesion layer and a diffusion barrier layer, wherein the Schottky electrode further includes a metal layer that prevents a reaction between the Schottky electrode and the diffusion barrier layer such that the metal layer is interposed between the top surface of the Schottky electrode and adhesion layer for increasing the distance between the diffusion barrier layer and the Schottky electrode.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Mitsuji Nunokawa, Yutaka Sato
  • Patent number: 6147488
    Abstract: A testing method for a magnetic recording medium which is magnetized measures variation of magnetization with the passage of time and evaluates the magnetic recording medium over its life. The method includes the steps of recording a first pattern at a density to be guaranteed in the magnetic recording medium, the first pattern having a difference between the sum total of areas of +bits and the sum total of areas of -bits, measuring remanence of the first pattern with the passage of time, and evaluating the magnetic recording medium over its life based on a measurement result.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Yasuo Bamba, Iwao Okamoto, Kazunori Yamanaka, Wataru Yamagishi
  • Patent number: 6147915
    Abstract: A semiconductor integrated circuit includes a plurality of circuits operating in parallel in accordance with a timing signal and having an enabled state and a disabled state, a control circuit setting each of the plurality of circuits to the enable state or the disabled state in accordance with an operation mode, and a timing adjustment circuit which adjusts the timing signal in accordance with a number of circuits which are in the enabled state.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Makoto Yanagisawa, Kazuyuki Kanazashi, Yuji Kurita
  • Patent number: 6148351
    Abstract: A protocol controller connected between a SCSI device and a DMA controller. The SCSI device is connected to the protocol controller with a first bus and the DMA controller is connected to the protocol controller with a second bus having a width less than a width of the first bus. The protocol controller communicates with the SCSI device so that it transfers data having a width equivalent to the width of the second bus. Other data concurrently transferred by the SCSI device over the first data bus is ignored and not transferred to the DMA controller.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Takase
  • Patent number: 6148185
    Abstract: The present invention relates to a feed-forward amplifying device suitable for radio communication systems such as digital automobile telephone.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Maruyama, Tokihiro Miyo, Fumihiko Kobayashi, Tatsuo Furukawa, Norio Tazawa, Yasushi Seino