Abstract: Data in a data base that describe a logic circuit are converted to a simulation model, and simulations are performed based on them. When it is desired to change a part of the circuit while a simulation is in progress, a tentative correction is made by directly changing the simulation model without entering logics to the data base again. Simulation is continued based on the changed simulation model, then, after the action has been confirmed, the contents of the change are reflected on the data base. In this way, a circuit can easily be changed while simulation is in progress.

Abstract: An optical pickup for writing/reading a magneto-optical signal recorded in a magneto-optical recording medium is provided, which reduces the size, integrates the functions and improves the mounting efficiency of a magneto-optical signal detection mechanism. The optical pickup comprises a semiconductor laser, a hologram for transmitting and diffracting the light emitted from the semiconductor laser, a collimator lens for condensing the light emitted from the semiconductor laser, an objective lens for condensing the laser light on an optical recording medium, a composite device interposed between the collimator lens and the objective lens, and photo-detectors for detecting an optical signal. The composite device 10 includes a polarization beam splitter 11, a condensation device 12, a reflector and a polarizer/splitter 14 integrated with each other. A photo-detector for detecting a servo signal and a photo-detector for detecting a magneto-optical signal are fabricated on a single substrate.

Abstract: A magnetoresistive transducer includes a multilayer provided with a first soft magnetic layer, a conductive nonmagnetic layer, a second soft magnetic layer, and a biasing magnetic layer giving a magnetization of a predetermined direction to the second soft magnetic layer, in that order of superposition. The first soft magnetic layer is a multilayer superposed structure including a (Co.sub.y Fe.sub.100-y).sub.100-x Z.sub.x alloy layer where Z represents boron and x and y represent atomic fractions (at %), and an alloy layer containing at least Ni and Fe. The (Co.sub.y Fe.sub.100-y).sub.100-x Z.sub.x alloy layer ofthe first soft magnetic layer borders on the nonmagnetic layer and has a face-centered cubic lattice structure with a d spacing smaller than a d spacing of a Co.sub.y Fe.sub.100-y alloy. A pair of electrodes are formed on the multilayer for allowing a sense current to pass through the multilayer.

Abstract: A cooling system for various electronic packages used in electronic equipment such as electronic computers, work stations, word processors, etc. and, particularly, a cooling system capable of efficiently cooling various electronic packages and, particularly, highly dense electronic packages used in electronic equipment without greatly limiting the freedom for designing the electronic equipment as a whole. The cooling system includes a heat radiator (40, 40', 40") installed in at least one independent holding portion formed in advance in a housing (30) of the electronic equipment, a heat conducting plate element (36) provided for at least one electronic package in said housing so as to receive heat therefrom, and a heat conducting passage element (38) laid down to conduct heat from the heat conducting plate element to a heat radiator.

Abstract: A program edit apparatus simply edits a program without making a programming mistake, even though the program is complicated. The program edit apparatus is provided with a source program storage part, a condition designation part, a display data generation part, and a display part. The source program storage part stores a source program, and the condition designation part designates one of the compile conditions contained in the source program. The display data generation part generates display data by extracting statements to be compiled in accordance with the compile condition designated by this condition designation part, and the display part performs display based on this display data. With this configuration, only statements relates to the compile condition are displayed on the display part.

Abstract: The carrier including a plurality of storage sections for individually accommodating electronic parts and a plurality of connecting sections for connecting the adjacent storage sections with each other. Each storage section is provided with a bottom wall and a side wall for defining a recess, and a support section for supporting the electronic part. The support section includes one rib continuously extending on the bottom wall along a generally rectangular profile, and a plurality of columnar projections projecting from the bottom wall to a height generally identical to one another and lower than a height of the rib. The bottom wall includes a first surface extending between the side wall and the rib to define a first region of the recess, and a second surface extending inside the rib to define a second region of the recess shallower than the first region. The columnar projections are arranged in a distributed manner on the second surface of the bottom wall.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: A cell flow rate control method for an ATM switch can cope with various UPC forms while using the same hardware arrangement. The cell flow rate control method includes the steps of preparing a conformance condition table in which are stored conformance conditions for each connection determined for each cell loss priority in an ATM cell; and employing, for each cell loss priority, a plurality of conformance test components in accordance with the conformance condition stored in the conformance condition table.

Abstract: A vertically aligned liquid crystal display device includes a liquid crystal layer of a negative dielectric anisotropy set to fall in a range between about -3.8 and about -2.

Abstract: If a context process range extending unit cannot obtain context information required by a context processing unit, from a range to be translated, it extends the context process range. Then, the context processing unit performs a context process, and passes extracted context information to a translation processing unit in order to perform translation, based on the extended context process range.

Abstract: Each servo disk is formed by obtaining an angle from a stopper space obtained by moving an actuator, further obtaining a feed pitch angle for each cylinder by a prespecified number of cylinders from the angle, and writing servo data thereon according to the pitch angle, so that a feed pitch angle becomes larger in association with a wider space between the stoppers, with which a larger track pitch for each cylinder can be insured.

Abstract: A clock matching apparatus for a data reproduction system includes a phase error detection unit which detects a phase error of a clock signal based on samples of a readout signal output by a sampler of the data reconstruction system. A phase-locked loop supplies a phase-matched clock signal to the sampler by compensating for the phase error detected by the phase error detection unit. The phase error detection unit includes an edge detection unit which detects a sampling instant for an edge sample among the samples of the readout signal. A difference unit generates a difference in timing phase between the edge sample and a sync level, the sync level being a reference signal level corresponding to a level of the readout signal at the sampling instants thereof and defined based on a partial-response waveform, the difference in the timing phase being output to the phase-locked loop as the detected phase error.

Abstract: In a magnetic tape drive for a single-reel type magnetic tape cartridge having a leader block coupled to a leading end of a magnetic tape wound therein, a hub for winding the tape pulled out of the cartridge is disposed at rear side of a magnetic head unit for writing data on and reading data from the tape, and has a radial slot formed therein for receiving the leader block of the tape threaded through the unit. The rotational direction of the hub is determined such that the leader block is subjected to an radially-inward force in the slot of the hub at the beginning of a rotational movement of the hub, whereby slippage of the leader block from the slot of the hub can be prevented.

Abstract: A device comprising an optical amplifier including an optical amplifying medium, and first and second optical filters operatively connected to the optical amplifier to suppress the wavelength dependence of gain. The medium has an input end and an output end for an optical signal. The medium is pumped so that it provides a gain band. The gain band includes a first band giving a relatively high gain and noise figure to the optical signal and a second band giving a relatively low gain and noise figure to the optical signal. The first optical filter is connected to the input end of the medium and has characteristics such that the first optical filter suppresses the wavelength dependence of gain in the second band. The second optical filter is connected to the output end of the medium and has characteristics such that the second optical filter suppresses the wavelength dependence of gain in the first band.

Abstract: Method and apparatus for extending lower-layer flow control end-to-end, transparent to network host systems, between network hosts attached to legacy networks without requiring any changes to the host networks or hosts themselves. In a first embodiment, a source host and a destination host, each residing on a respective LAN, communicate via an intermediate network supporting the lower-layer flow control. A higher-layer, end-to-end flow control protocol exists between the hosts. The lower-layer flow control protocol accounts for loss of bandwidth between each hop within the intermediate network. To extend the lower-layer flow control protocol to the hosts, an intelligent edge device of the intermediate network adjusts observed higher-layer flow control parameters based upon the state of the lower-layer flow control. No modifications to the legacy network or hosts is required, and the extension of flow control is transparent to the legacy networks.

Abstract: A clock supplying circuit that supplies a clock to a plurality of controlled circuits 451-454 arranged in respectively different positions. A forward and backward wiring 41, 42 and an internal clock supply wiring 43 are arranged along controlled circuits. A main clock drive circuit 40 is for outputting a first clock to the forward wiring 41 and is for outputting a second shorter phase than the first clock to the internal clock supply wiring 43. A plurality of local clock drive circuits 441-444 arranged close to the controlled circuits, are supplied with a forward clock propagated along the forward wiring and with a back clock propagated along the backward wiring, and are also supplied with the second clock, for delaying the phase of the supplied second clock so as to coincide with a phase intermediate the forward clock and the back clock, and for supplying the delayed clock of the second clock to the respectively corresponding controlled circuits as local clock.

Abstract: A direct-sense activation circuit 20 is provided for a sense circuit row 12A. When a memory block 0 is activated, the direct-sense activation circuit 20 activates a direct-sense driving line in response to an activated read signal from the control circuit 18. The direct sense circuit is provided with a direct sense gate which is controlled by the voltage of a bit line and a column gate connected to the direct sense gate in series between the direct-sense driving line and a read-data bus line. A plurality of memory blocks are disposed in the direction perpendicular to the sense circuit row 12A, a column decoder 13 and a sense buffer circuit 15 are disposed so that these memory blocks are placed therebetween, and the word decoders are disposed on a side of the respective memory blocks.

Abstract: A signal reproducing circuit includes first power supply lines having different potentials, a magneto-resistive effect head having one end thereof coupled to the first power supply line, for reproducing data recorded on a magnetic recording medium in a read operation, and a first constant current source coupled between another end of the magneto-resistive effect head and the second power supply line, for supplying the magneto-resistive effect head with a sense current in the read operaion. Also included are first and second transistors having collectors thereof coupled to the first power supply line, respectively, and responsive to voltage signals obtained from the one end and the other end of the magneto-resistive effect head.

Abstract: A direct-current to direct-current conversion (DC/DC) apparatus includes a control circuit having an error amplifier for voltage control and controlling a direct-current to direct-current conversion based on a pulse width modulation control using an output of the error amplifier. The error amplifier inputs a voltage signal corresponding to an output voltage of a DC/DC result and a plurality of reference voltage signals. The DC/DC apparatus also includes a soft start capacitor to provide one of the plurality of reference voltage signals. The error amplifier amplifies a difference between the voltage signal corresponding to the output voltage of a DC/DC result and a voltage signal of a lower potential among the plurality of reference voltage signals and, based on the amplified output, carries out the pulse width modulation control.

Abstract: In a parallel computer system using a SIMD method constituted by a controller and a plurality of processor elements, each of the processor elements has a storage unit to store data to be processed, the controller controls operation of the processor elements, and the parallel computer system performs processing of the data based on a calculation control signal transmitted from the controller. The parallel computer system further a data collection unit connected between the processor elements and the controller for receiving output data from the processor elements, performing a predetermined calculation, and outputting calculated data to the controller; and a calculation control unit connected between the data collection unit and the controller for transmitting the calculation control signal from the controller to the data calculation unit to make it possible to perform the predetermined calculation in the data collection circuit.