Patents Assigned to Fujitsu
  • Patent number: 6157506
    Abstract: A write signal is examined so as to recognize occurrence of magnetization reversal for a first bit to be recorded, a second bit preceding the first bit and a third bit preceding the second bit. A write signal reversal for the first bit is delayed by a first delay when the second bit has an associated write signal reversal and when the third bit does not have an associated write signal reversal. A write signal reversal for the first bit is delayed by a second delay set to be smaller than the first delay, when the third bit has an associated write signal reversal and when the second bit has an associated write signal reversal, and a write signal reversal for the first bit is delayed by a third delay set to be smaller than the second delay, when the third bit has an associated write signal reversal and when the first bit does not have an associated write signal reversal.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventor: Hiroaki Ueno
  • Patent number: 6157068
    Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Koichi Hashimoto, Hiromi Hayashi
  • Patent number: 6156646
    Abstract: A method of manufacturing a semiconductor device is provided in which a well patterned lead line structure is obtained. In one aspect of the invention, the method comprises steps of:depositing on a semiconductor wafer a metal layer for forming lead lines at a first predetermined temperature of about 400.degree. C., say; anddepositing an anti-reflective layer on the metal layer in the following multi-deposition steps:step 1: a thin anti-reflective layer is deposited on the metal layer near the first predetermined deposition temperature;step 2: the metal layer is cooled to a second predetermined deposition temperature of about 150.degree. C., say while interrupting the deposition of the anti-reflective layer; andstep 3: the anti-reflective layer is grown to a predetermined thickness by resuming the deposition thereof at the second predetermined deposition temperature.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventor: Yukihiro Ishihara
  • Patent number: 6158038
    Abstract: An error correcting method reducing the time needed to provide error correction using a buffer memory. The method includes performing row error correction by using a plurality of rows of data to produce row-corrected block data and performing column error correction by using the plurality of columns of data to produce column-corrected block data. In addition, at least one of the performing row error correction and performing column error correction operates using a plurality of rows or columns of data in units of a predetermined number of rows or columns so as to provide error correction for the plurality of rows or columns in parallel.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirofumi Yamawaki, Masashi Yamawaki, Kenichi Yamakura
  • Patent number: 6157518
    Abstract: A magnetic head slider includes a pair of rails formed on a disk opposing surface opposed to a magnetic disk, each of the rails having a flat air bearing surface for generating a flying force during rotation of the disk, a slit formed between the pair of rails at their air inlet end portions, and a groove defined between the pair of rails which is continuous to the slit and wider than the slit, for expanding the air once compressed to generate a negative pressure. The magnetic head slider further includes an electromagnetic transducer formed on an air outlet end at a position where one of the rails is located. The slider has a trapezoidal shape such that its air inlet end is narrower than its air outlet end.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Ryosuke Koishi, Seiji Yoneoka
  • Patent number: 6157481
    Abstract: An optical amplifying apparatus which includes an optical amplifier, an optical attenuator and a controller. The optical amplifier amplifies a light signal having a variable number of channels. The optical attenuator passes the amplified light signal and has a variable light transmissivity. Prior to varying the number of channels in the light signal, the controller varies the light transmissivity of the optical attenuator so that a power level of the amplified light signal is maintained at an approximately constant level that depends on the number of channels in the light signal prior to the varying the number of channels. While the number of channels in the light signal is being varied, the controller maintains the light transmissivity of the optical attenuator to be constant.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Yasushi Sugaya, Susumu Kinoshita
  • Patent number: 6158009
    Abstract: A communication monitoring and controlling apparatus for easily collecting monitoring information is connected to an existing network composed of a plurality of communication equipment. A management information collecting unit collects management information of each of the communication equipment. The management information is in an existing network management information format. A format converting unit converts the management information in the existing network management information format into management information in a new-type network management information format. The new-type network management information format is a format used by the new-type network, and handles the existing network composed of the communication equipments as one network element. The converted management information is transmitted to at least one operation system of the new-type network by a transmitting unit.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Ichiro Ayukawa, Yuji Shiraishi, Yoshiko Koizumi, Kazutoshi Kawamura, Kimio Watanabe
  • Patent number: 6157947
    Abstract: A distribution apparatus is used to distribute intellectual property to be reused for semiconductor product designing. The distribution apparatus has a memory portion for registering intellectual property, users, and services available for the users, a processing portion for providing a user with a service allowed for the user, and a communication portion for automatically distributing the intellectual property. The distribution apparatus enables users to receive information about the intellectual property on time and to optimally share the intellectual property.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Yoshiaki Watanabe, Shigeyo Iino, Yasuaki Morita, Kazuhiro Nishimori, Ichiro Kijima
  • Patent number: 6156141
    Abstract: A method for forming a plurality of stripe-like phosphor layers on a surface of a substrate constituting a plasma display panel, the surface having a plurality of parallel ribs disposed thereon and grooves defined between two adjacent ribs, includes the steps of: molding a phosphor paste composed of a phosphor substance and a first synthetic resin into filament-like article; placing the molded filament-like article into each groove; filling the grooves with a solvent optionally containing a second synthetic resin compatible with the first synthetic resin; and conducting a sintering treatment of the substrate to form the phosphor layers in the grooves.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventor: Yoshimi Shirakawa
  • Patent number: 6156662
    Abstract: A method of fabricating a liquid crystal display device includes the step of removing a porous anodic oxide film selectively with respect to a barrier-type anodic oxide film covering a gate electrode pattern of a thin-film transistor, wherein the step of removing the porous anodic oxide film is conducted after the step of disconnecting a bridging conductor pattern used for supplying electric current at the time of anodic oxidation process of the gate electrode.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Ohori, Tamotsu Wada, Kohji Ohgata, Tatsuya Kakehi, Ken-ichi Yanai
  • Patent number: 6156259
    Abstract: In a method of manufacturing piezoelectric ceramics by molding pre-fired or calcined powders of ingredients of a piezoelectric ceramic material and sintering the powder mold at a high pressure, the powder mold is pre-sintered at an atmospheric pressure before sintering at high pressure (HIP). Preferably, after the sintering HIP step, a thermal treatment is performed at a temperature of from 500 to 1000.degree. C. under an oxidizing atmosphere. For a Pb(Zn.sub.1/3 Nb.sub.2/3)O.sub.3 --PbTiO.sub.3 based piezoelectric ceramic, the composition is preferably set to (Pb.sub.1-x Ba.sub.x)[(Zn.sub.1/3 Nb.sub.2/3).sub.1-y Ti.sub.y ]O.sub.3, where 0.001<x<0.055 and 0.05<y<0.20.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Motoyuki Nishizawa, Mineharu Tsukada, Kaoru Hashimoto, Nobuo Kamehara
  • Patent number: 6157688
    Abstract: A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirotaka Tamura, Miyoshi Saito, Kohtaroh Gotoh, Shigetoshi Wakayama, Junji Ogawa, Hisakatsu Araki, Tsz-shing Cheung
  • Patent number: 6157128
    Abstract: A plasma display panel includes a pair of substrates and electrodes extending in row direction of display to generate a surface discharge across a pair of the electrodes. In the panel, at least one electrode of the electrode pair for generating the surface discharge is formed in the shape of a comb having a base portion extending in row direction of display and a tooth portion composed of a number of teeth extending from the base portion towards the other electrode. And an arrangement pitch of the teeth is 1/n of an arrangement pitch of cells in row direction of display, in which n is an integer more than or equal to two.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Fumihiro Namiki, Shigeo Kasahara
  • Patent number: 6157523
    Abstract: A spin valve magnetoresistive head includes a first soft magnetic layer and a second soft magnetic layer having larger internal stress than that of the first magnetic layer. The larger internal stress of the second soft magnetic layer is created by injecting the second soft magnetic layer with a selected type of ion. Also included in the head is a nonmagnetic layer formed between the first soft magnetic layer and the second soft magnetic layer.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Hideyuki Kikuchi, Kazuo Kobayashi, Hitoshi Kishi, Mitsuru Otagiri
  • Patent number: 6157685
    Abstract: A multistage interference canceller equipment and interference canceller method for use, for example, in CDMA (Code Division Multiple Access) multibeam-antenna communication system includes in each stage an interference canceller unit which has a replica signal generator which generates from an input beam signal a first interference replica signal and outputs a first error signal, and an interference removal unit which receives from another replica signal generator a second interference replica signal, multiplies that second interference replica signal by conversion coefficients and subtracts an obtained signal from the first interference replica signal to produce a second error signal so that an error signal is generated for each signal beam from the interference replica signals of a local signal beam and other signal beams to eliminate interference.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Yoshinori Tanaka, Shuji Kobayakawa, Hiroyuki Seki, Takeshi Toda, Masafumi Tsutsui
  • Patent number: 6157599
    Abstract: In a low speed seek control unit, when it is judged by an error detection judging unit that a zero-cross error detection has occurred during a seeking operation, a speed prediction calculating unit predictively calculates a correct speed on the basis of the last track zero-cross interval free from any error detection and supplies the predicted speed in place of a detected speed to a speed control unit for the execution of a speed control, while a counter modification unit returns a track counter so as to have a value before the error detection. In a high speed seek control unit, when it is judged by an error detection judging unit that a zero-cross error detection has occurred, a speed prediction calculating unit predictively calculates a correct speed and supplies the predicted speed in place of a detected speed to a speed control unit for the execution of a speed control, while a counter modification unit modifies a track counter so as to have a correct value.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: December 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Tomonori Yamashita, Shigenori Yanagi
  • Patent number: 6153897
    Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 6154047
    Abstract: A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventor: Masao Taguchi
  • Patent number: 6153511
    Abstract: A method of making a semiconductor device has a multilayer interconnection structure including a lower organic interlayer insulation film, an etching stopper film on the lower interlayer insulation film and an upper organic interlayer insulation film covering the etching stopper film, wherein the upper organic interlayer insulation film is covered by first and second etching stopper films of respective, different compositions.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventor: Hirofumi Watatani
  • Patent number: 6154808
    Abstract: A semiconductor memory device has a memory space which includes blocks and each of the blocks includes sectors. The sectors have a data storing region and a flag region. Data stored in a sector is marked as valid or erased, depending on the flags in the flag region. If an even number of the flags in the flag region have a logical value of 1, the data is considered to be erased. The data in each sector may be erased and unerased a number of times, by sequentially altering the value of the flags in the flag region. Data stored in the memory may be erased on a sector-by-sector basis.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventors: Takeshi Nagase, Shinpei Komatsu, Yoshihiro Takamatsuya