Abstract: Methods and apparatus, including computer program products, implementing and using techniques for reducing the power consumption of a microprocessor. One or more signal transitions in an instruction set of a microprocessor are profiled. A probability of occurrence is assigned to each instruction in the instruction set. A binary operation code is assigned to each instruction, based on the probability of occurrence for the instruction. The instructions having the highest probability of occurrence are assigned operation codes that require fewer signal transitions. As a result, the power consumption of the microprocessor is reduced.

Abstract: The present invention provides polypeptides comprising an immunogenic epitope of a M. vaccae protein, polynucleotides encoding such polypeptides, and fusion proteins comprising at least one such polypeptide, together with genetic constructs comprising at least one inventive polynucleotide. Compositions comprising such polypeptides, polynucleotides, fusion proteins and/or genetic constructs may be employed in the treatment of infectious diseases and immune disorders.

Abstract: Detecting when the on-board power supply is powered on or off by an auto activity detection circuit by determining if the reference clock signal (TCLK) is toggling and if the reference clock signal is toggling, then charging a capacitor to a high voltage in the auto activity detection circuit based on the toggling reference clock signal, and outputting an on-board power supply activity signal based upon the high voltage by the auto activity detection circuit indicative of whether or not the on-board power supply is active

Abstract: The present invention includes a harvesting and irrigation device, a method and a kit for the collection of viable fat cells and/or adipose tissue with decreased handing and improved yield and viability.

Abstract: A method of automatic gain control in both analog and digital domain is performed by receiving an incoming analog signal, determining an overall gain factor, determining a coarse analog gain control value and a fine digital gain control value, each of which, when taken together substantially equals the already determined overall gain factor, modifying the incoming analog signal using the coarse analog gain control value to form a coarsely adjusted digital signal, digitizing the coarsely adjusted digital signal, and using the fine digital gain control value to process the coarsely adjusted digital signal to form an outgoing digital signal, wherein the outgoing digital signal has been modified in both the analog domain and subsequently in the digital domain to achieve an appropriate signal to noise ratio.

Abstract: A method, system and apparatus for synchronizing an analog video signal to an LCD monitor is described. For each of a succession of associated video frames are surveyed for a number of displayed features based upon a pseudo-random selection of regions into which the displayed video frame is divided. During successive associated video frames, a minimum number of features each is which is generated by an associated pixel clock is determined based upon a pre-selected number of scans. Subsequent to the determination of the minimum number of features, a transition region for each of plurality of horizontal resolution values is determined by scanning through a selected number of pixel clock phases. Based upon a minimum transition zone corresponding to a maximum change in the number of features for a particular pixel clock phase, an associated horizontal resolution is provided.

Abstract: Automatically and adaptively controlling contrast and color of a display device by computing a normalized histogram of a current image, computing degrees of correlation between the normalized histogram and a number of template histograms, sorting the template histograms based upon the associated degrees of correlation, selecting a number of the best correlated template histograms based on the sorting, blending the selected the transfer functions associated with the selected template histograms to form a blended transfer function, and applying the blended transfer function to the current image.

Abstract: In digital display circuitry, configured to display an image encoded in an analog display signal, the digital display circuitry includes analog-to-digital converter (ADC) circuitry to recover pixel data elements of the image. During vertical blanking intervals of the analog display signal, the ADC circuitry is calibrated. Outside the vertical blanking intervals, the ADC circuitry is used to convert information in the analog display signal into digital representations of the pixel data elements. For example, the calibrating may include determining more acceptable values for certain ones of the operational parameters of the ADC circuitry.

Abstract: A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.

Abstract: The invention relates to a light-emitting element with porous light-emitting layers. The light-emitting element comprises: a substrate, a first conductive cladding layer, a second conductive cladding layer and at least one porous light-emitting layer. The porous light-emitting layer is formed between the first conductive cladding layer and the second conductive cladding layer, and has an upper barrier layer, a lower barrier layer and a carrier trap layer. The carrier trap layer positioned between the upper barrier layer and the lower barrier layer has a plurality of chevron structures for defining a plurality of valley shaped structures, and is an indium-containing nitride structure, the energy band gap of which is less than those of the upper barrier layer and the lower barrier layer.

Abstract: A display controller includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device that is always available for access by the data ports and/or the processor regardless of a power state of the display controller, a data buffer for storing EDID read from the memory device, and an arbitration circuit for arbitrating memory device access requests between the processor and a requesting data port wherein when the data buffer is not almost empty, then the arbitration circuit grants the processor access to the memory wherein when the data buffer is almost empty, then the arbitration circuit grants only the requesting data port access to them memory so as to replenish the data buffer with read EDID.

Abstract: In a VESA standard compliant display controller having a processor arranged to process executable instructions and associated data, a memory device arranged to store EDID and the executable instructions and associated data, a number of data ports coupled to the memory device by way of an 12C data bus each coupled to a host device, a method of transferring EDID from the memory device over the 12C data bus to a requesting one of the data ports while servicing a processor memory access request without clock stretching.

Abstract: A transmission efficient packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed. The transmission efficient interface includes a bi-directional auxiliary channel arranged to transfer information between the multimedia source device and the multimedia sink device and vice versa, wherein the information transferred over the auxiliary channel includes a set of packet attributes. The interface also includes a unidirectional main link arranged to carry a number multimedia data packets from the transmitter unit to the receiver unit each having a multimedia data packet header. In the described embodiment, each of the headers is substantially reduced in size over what would otherwise be necessary since the packet attributes are communicated via the auxiliary channel prior to the transmission of the main link packets over main link thereby minimizing the packet overhead and providing a very high main link efficiency.

Abstract: A digital filter includes a plurality of connected component digital filters. Control signal generation circuitry is configured to receive a tap output signal from each of at least some of the component digital filters and to process the received tap output signals to generate a control signal to output from the control signal circuitry. Output processing circuitry is configured to process an output of one of the plurality of component digital filters, based on the control signal generated by the control signal circuitry, to generate an output of the digital filter. The processing of the received tap output signals by the control signal generation circuitry may be, for example, programmably configurable.

Abstract: Managing power in a display controller having an on-board power supply coupled to a host device having an off-board power supply by way of a connector is described. If the on-board power supply is active, then power is supplied to the display controller by the off-board power supply by way of the connector and a low frequency clock arranged to provide a low frequency clock signal is turned on. Alternatively, when it is determined that the on-board power supply is active, then power is supplied to the display controller by the on-board power supply only, the low frequency clock is turned off and a high frequency clock arranged to provide a high frequency clock signal is turned on.

Abstract: A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.

Abstract: Frequency content motion detection is performed by decomposing a raw field luminance data in to a number of frequency content sub-bands, detecting motion using the raw field luminance data in parallel with the decomposing, generating a motion correction value by multiplying absolute values of the sub-bands by weighting factors, and applying the motion correction value to detected motion.

Abstract: A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.

Abstract: A fuel cell power system has a fuel cell capable of generating electrical power, a battery holder releasably mounting at least one rechargeable battery, and a power controller which receives the electrical power from the fuel cell and distributes the electrical power to an output bus for use by an external load and to the battery for charging the battery. The rechargeable batteries may be easily inserted and removed from the system, with the batteries providing start-up power for the fuel cell power source, as well as surge power when the external electrical load is connected to the power system, or when the load exceeds the capacity of the fuel cell.

Abstract: A probe device having a contact probe including a film, a plurality of wiring patterns formed on the film with each wiring pattern having a front end portion projecting from the film so as to form contact pins, and a metal layer provided on the film. In one embodiment, the contact probe device includes first and second contact probes connected to each other, the first contact probe including a first film, and a plurality of first wiring patterns formed on the first film, each first wiring pattern having a front end portion projecting from the first film so as to form contact pins. The second contact probe includes a second film, and a plurality of second wiring patterns formed on the second film. The plurality of second wiring patterns are connected to the plurality of first wiring patterns, and the second contact probe is formed separately from the first contact probe.