Abstract: A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Abstract: A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.

Abstract: An adjustable signal equalization device includes an equalizer circuitry, an analog-to-digital converter (ADC), a calculation circuitry, and a comparator circuitry. The equalizer circuitry has a transfer function, and processes an input signal based on the transfer function to generate an output signal. The ADC generates a digital signal according to the output signal. The calculation circuitry performs an accumulation according to the first digital signal to generate a first accumulated value and a second accumulated value, and generates a first detection signal and a second detection signal according to the first accumulated value and the second accumulated value. The comparator circuitry compares the first detection signal with the second detection signal to output a control signal to the equalizer circuit if the first detection signal is different from the second detection signal, in order to adjust the transfer function.

Abstract: A probe card device includes a testing circuitry board, a flexible probe needle, a first solder portion, a second solder portion and an interconnected holder electrically connected to the testing circuitry board and the flexible probe needle in which one end of the interconnected holder is coupled to the flexible probe needle with the first solder portion, and the other end of the interconnected holder is coupled to a conductive pad of the testing circuitry board with the second solder portion. A first desoldering melting point of the first solder portion is higher than a second desoldering melting point of the second solder portion.

Abstract: An embodiment of the present disclosure provides a damping component. The damping component includes a housing, at least one sliding piece, a fluid, and at least one damping elastomer. The housing may have at least one opening. The sliding piece slidably seals the opening, and partially protrudes outside the opening, to form an accommodation space within the housing. The fluid can fill up the accommodation space. The damping elastomer can be disposed inside the accommodation space.

Abstract: A probe card and a testing method are disclosed herein. The probe card includes a plurality of probe sets arranged as a testing unit. The testing unit is configured to test a plurality of dies in a test region on a wafer, and to move m unit along a first direction and n unit along a second direction when the test complete so as to test the next test region, in which m and n are integers.

Abstract: A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.

Abstract: An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result.

Abstract: A clock and data recovery (CDR) circuit is provided, and includes a sampling circuit, an error sampler, a phase detect circuit, and a phase adjust circuit. The sampling circuit generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect circuit receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect circuit stops transmitting the corrective signal. The phase adjust circuit generates and adjusts the first and the second clock signal according to the corrective signal.

Abstract: An image correction system includes a storage device and a processor. The storage device is configured to store multiple reference patterns corresponding to different color temperatures. The processor is configured to execute operations of receiving an input image and correspondingly transforming the input image into multiple input gamut points; generating an input pattern according to distribution of the input gamut points, in which the input gamut points are surrounded by the input pattern; comparing the input pattern with the reference patterns to generate a comparison result; and estimating out a color temperature corresponding to the input image according to the comparison result so as to correct the input image.

Abstract: A brightness calibration method used in an optical detection system includes a single source illuminator and a probe card. The single source illuminator is configured to illuminate the probe card. The probe card has a plurality of detection sites. The brightness calibration method includes: sequentially detecting brightness values at the detection sites through one of a plurality of diffusers by a sensing chip; sequentially detecting transparencies of the diffusers at one of the detection sites by the sensing chip; and selecting and respectively disposing the diffusers corresponding to larger ones of the transparencies over the detection sites corresponding to smaller ones of the brightness values, and selecting and respectively disposing the diffusers corresponding to smaller ones of the transparencies over the detection sites corresponding to larger ones of the brightness values.

Abstract: A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Abstract: A multilayer laminated substrate structure includes plural substrate layers stacked with each other, and a conductive via portion. One of the substrate layers is provided with a through hole. The conductive via portion includes a first signal conductive pad having a first rib, a second signal conductive pad having a second rib, and a conductive body which is disposed in the through hole and is electrically connected to the first rib and the second rib. The first signal conductive pad and the second signal conductive pad are disposed on two opposite surfaces of the substrate layer, and the first rib and the second rib are arranged in a staggered manner in relation to each other.

Abstract: A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.

Abstract: An optical inspection fixture includes a first bracket, a second bracket and at least one loading surface. The first bracket is provided with at least one first arm. The second bracket and the first bracket are separated from each other so as to define a light traveling path that lights can go through. The second bracket is provided with at least one second arm which is separated from the first arm. The loading surface is between the first bracket and the second bracket, and connected to at least one of the first arm and the second arm, and the loading surface is used to carry an optical conversion element.

Abstract: A common-mode filter includes a first transmission line, a second transmission line, a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer includes a first conductive capacitor plate, in which at least partial first transmission line is in the first wiring layer, and electrically coupled with the first conductive capacitor plate. The second wiring layer includes a second conductive plate and a first inductor, and the second conductive capacitor plate is electrically coupled with the first inductor. The third wiring layer includes a third conductive capacitor plate, in which at least partial second transmission line is in the second wiring layer, and electrically coupled with the third conductive capacitor plate. The first conductive capacitor plate at least partial faces the second conductive capacitor plate, and the second conductive capacitor plate at least partial faces the third conductive capacitor plate.

Abstract: A timing analysis method for a digital circuit design, a system and a computer readable storage media thereof are provided. The timing analysis method includes following steps. An integrated circuit (IC) design is obtained, wherein the IC is operated in a plurality of operating modes. A plurality of extracted timing models (ETMs) are respectively generated according to the operating modes of the IC design, wherein each of the ETMs includes a none on-chip variation (NOCV) part and an on-chip variation (OCV) part. The ETMs corresponding to the operating modes are integrated into a NOCV ETM and an OCV ETM, wherein the OCV part of the operating modes is not considered when the NOCV ETM is generated. And, a timing checking of the IC design is analyzed according to the NOCV ETM and the OCV ETM.

Abstract: A probe card includes a circuit board, a plurality of probes, and at least one deviation-compensating member. An end of each of the probes is connected to the circuit board. The deviation-compensating member is fixed to the circuit board and connected to the probes. The probes have a first thermal expansion characteristic, the deviation-compensating member has a second thermal expansion characteristic, and the first thermal expansion characteristic and the second thermal expansion characteristic are different.

Abstract: A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Abstract: An aging detection circuit is provided. The aging detection circuit is configured on a chip and includes a testing circuit and an aging signal generation circuit. The testing circuit is electrically coupled to the aging signal generation circuit. The testing circuit generates an output signal. The aging signal generation circuit includes a signal generation circuit and a selection circuit. The signal generation circuit generates multiple input signals having different frequencies. The selection circuit selectively outputs one of the input signals as an aging signal to an input terminal of the testing circuit or feeds back the output signal generated by the testing circuit to the input terminal of the testing circuit.