Abstract: A carrying device includes a main body, a grasping portion, a heat-exchanging module and a gas chamber device. The grasping portion is connected to the main body for grasping a semiconductor element. The heat-exchanging module is disposed on the main body. The gas chamber device includes a case body and a gas. The case body is disposed between the grasping portion and the heat-exchanging module, and has a closed chamber therein. The gas fills the closed chamber for transferring heat from the semiconductor element to the heat exchanging module, in which a specific heat capacity of the gas is about between 5000 J/(kg·K)-15000 J/(kg·K).

Abstract: A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.

Abstract: A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

Abstract: A device for generating a duty cycle includes a converter, a corrector, and a control circuit. The converter is configured to generate a first output signal having a duty cycle to an output terminal according to an input signal. The corrector is coupled to the output terminal, and is configured to adjust the duty cycle of the first output signal according to a control signal. The converter is coupled in parallel with the corrector and between a first power source and a second power source. The control circuit is coupled to the output terminal, and is configured to generate the control signal according to the first output signal and a reference signal.

Abstract: An integrated circuit, a multi-channel transmission apparatus, and a signal transmission method thereof are provided. The multi-channel transmission apparatus includes a pre-stage circuit, a clock signal generator, and a post-stage circuit. The pre-stage circuit receives a plurality of first clock signals and a plurality of data signals, selects one of the first clock signals to be a base clock signal, and transmits the data signals according to the base clock signal to respectively generate a plurality of middle signals. The clock signal generator generates the first clock signals according to a second clock signal, wherein a frequency of the second clock signal is higher than a frequency of the first clock signals. The post-stage circuit transmits the middle signals according to the second clock signal to respectively generate a plurality of output signals. The pre-stage circuit is a digital circuit, and the post-stage circuit is an analog circuit.

Abstract: A clock and data recovery device includes a data analysis circuitry, a loop filter circuitry, a phase rotator circuitry, a multiplexer circuitry, and a phase interpolator circuitry. The data analysis circuitry analyzes input data according to a first clock signal and a second clock signal to generate an error signal. The loop filter circuitry updates an adjustment signal according to the error signal. The phase rotator circuitry adjusts rotation signals according to the adjustment signal and limit values if the adjustment signal is updated. The multiplexer circuitry outputs one of the rotation signals as a phase control signal according to third clock signals. The phase interpolator circuitry adjusts the first and the second clock signals according to the phase control signal and fourth clock signals.

Abstract: A testing device includes a circuit board, a carrier, a probe pin, a main body, a shaft, a pressing portion and a resilient spiral spring. The carrier is used to hold a device under test (DUT). The probe pin is electrically connected to the circuit board and the DUT. The shaft is movably connected to the main body with a screwing rotation method. The pressing portion is connected to one end surface of the shaft. The resilient spiral spring is retractably coiled on the shaft, and one end of the resilient spiral spring being far away from the shaft extends in a transverse direction intersecting an axial direction of the shaft.

Abstract: A method for utilizing a probe card includes steps as follows. Providing a probe card having three alignment marks on a reference plane of a circuit board; moving the circuit board to be oriented to a wafer-loading plane of a wafer stage with the reference plane; determining whether a geometric plane defined by the alignment marks is parallel to the wafer-loading plane; and when the geometric plane is not parallel to the wafer-loading plane, adjusting a levelness of the circuit board until the reference plane is parallel to the wafer-loading plane.

Abstract: A wafer shipping device includes a box body having a first slot, a cover body having a second slot, and a sensing circuit module having a first sensor, a second sensor, an indication circuit and a warning device. The first slot and the second slot are used to collaboratively hold a semiconductor wafer. The first sensor and the first sensor are located in the box body for independently sensing whether the semiconductor wafer is inserted in the first slot and the second slot respectively. The indication circuit is electrically connected to the first sensor, the second sensor and the warning device, and correspondingly issued one of types of indication signals to the warning device in response to sensing results obtained from the first sensor and the second sensor respectively.

Abstract: An analog-to-digital converter (ADC) device includes analog-to-digital converter circuitries and a data output circuitry. The ADC circuitries correspond to channels respectively, and convert an input signal to generate quantization outputs according to interleaved clock signals, wherein each of the interleaved clock signals has a sampling frequency. The data output circuitry performs a down-sampling operation according to a first control signal and the quantization outputs, in order to generate a digital signal. The first digital signal is for determining a performance of the ADC circuitries, and a frequency of the digital signal is N/M times of the sampling frequency, and N is a positive integer and is a number of the channels.

Abstract: A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.

Abstract: A probe loader device includes a carrier board, a three-dimensional stepped structure and a probe module having a plurality of probe pin layers separately stacked together in three-dimensional stepped structure. The three-dimensional stepped structure is connected to the carrier board. Each of the probe pin layers includes a plurality of cantilever probes. The cantilever probes respectively extend outwards from different steps of the three-dimensional stepped structure, and physical touch a plurality of electrical contacts of a DUT. A portion of each of the cantilever probes extending outwards from the three-dimensional stepped structure has a moment length, and the moment lengths of the cantilever probes of the different probe pin layers are the same.

Abstract: A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.

Abstract: A measurement system of a data transmission interface includes a signal generator and a signal receiver. The signal generator transmits an input data to the data transmission interface. The signal receiver receives an output data from the data transmission interface. The signal receiver measures a jitter tolerance capability of the data transmission interface according to error feedback data of the output data. The data transmission interface includes a receiving circuit, a synchronous circuit, and a transmitting circuit. The receiving circuit receives the input data and generates an error signal when a data error occurs. The synchronous circuit receives the error signal to generate an error indication signal. The transmitting circuit transmits the output data to the signal receiver and receives the error indication signal when the data error occurs, in order to generate the error feedback data in the output data according to the error indication signal.

Abstract: An ADC calibration system includes a clock generating circuit, under test ADCs, a standard ADC, and a calibration circuit. The clock generating circuit generates operation clocks according to a system clock, and generates a calibration clock according to the system clock and a selection signal. The under test ADCs sample an input signal according to the operation clocks to output under test sampling results. The standard ADC samples the input signal according to the calibration clock to output a standard sampling result. The calibration circuit makes the phases of the calibration clock and a first operation clock received by a first ADC to be the same. The calibration circuit compares the standard sampling result with a first under test sampling result to generate calibration information corresponding to the first under test sampling result, and calibrates the first under test sampling result according to the calibration information.

Abstract: A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

Abstract: An electronic device having active heat dissipation includes a wiring board, a semiconductor package unit, a surrounding unit, a fan module and a tube member. The semiconductor package unit is soldered to the wiring board through three-dimensional contacts. The surrounding unit is connected to the wiring board and the semiconductor package unit, and surrounds the three-dimensional contacts, such that a heat exchange space is collectively defined by the surrounding unit, the wiring board and the semiconductor package unit. The surrounding unit is provided with two openings which are in communication with the heat exchange space. The fan module is located outside the heat exchange space, and is connected to one of the openings.

Abstract: A method for determining performance of an integrated circuit (IC) is disclosed herein. The method includes following operations: disposing hardware performance monitors (HPMs) in each of ICs, in which each of HPMs generates a value for generating the performance of the IC; providing a performance function including of terms according to values generated by the HPMs, in which a weight is associated with each of terms; determining the weight of each of terms according to a first set of ICs of the ICs, wherein the performance of each of the ICs is known; and determining the performance of a first ICs of the ICs according to the performance function, wherein the performance function and the weights are built into the first ICs.

Abstract: A probe connector includes a probe body, a flexible sleeve body, a slit and a conductive fluid. The flexible sleeve body is connected to the probe body. The conductive fluid is received in the flexible sleeve body and electrically connected to the slit and the probe body. The slit is formed on one end of the flexible sleeve body opposite to the probe body, so as to define petal portions which are configured to be tightly closed together. When the slit is pressed to separate the petal portions, a portion of the conductive fluid seeps up from the flexible sleeve body via the slit.

Abstract: A cleaning apparatus includes a case and a cleaning head. The cleaning head is disposed on the case, and provided with a plurality of tines. The tines are separately arranged abreast. The tines are used to extend into gaps between plural conductive terminals of a semiconductor product for cleaning the semiconductor product.