Patents Assigned to GlobespanVirata
  • Patent number: 7177910
    Abstract: The present invention is directed to a system and method for communicating in a point to multipoint DSL communication network. Preferably, the point to multipoint communication network is established in the environment of a home or small office, and the invention is realized through a computer that may dynamically establish both LAN and WAN communications. Broadly, the system and method are realized by a computer that is configured to assume a role as either a Master or a Slave on a LAN. If the computer is the first (or only) computer powered up on the LAN, then it assumes the role of Master. In this role, the computer establishes a communication link with a WAN (such as with an Internet Service Provider), and directs all WAN communications over the WAN, using a WAN frequency and protocol (such as DSL). As other computers join the LAN, then WAN communications from those computers are relayed through the Master to the WAN. These communications are relayed to the Master using a LAN frequency band.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: February 13, 2007
    Assignee: GlobespanVirata, Inc.
    Inventor: Russell W. Bell
  • Patent number: 7013271
    Abstract: A method and system for implementing a low complexity spectrum estimation technique for comfort noise generation are disclosed. Another aspect of the present invention involves segregating filter parameter encoding from an adaptation process for transmission in the form of silence insertion descriptors. A method for implementing a spectrum estimation for comfort noise generation comprises the steps of receiving an input noise signal; approximating a spectrum of the input noise signal using an algorithm over a period of time; detecting an absence of speech signals; and generating comfort noise based on the approximating step when the absence of speech signals is detected; wherein the spectrum of the input noise signal is substantially constant over the period of time.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: March 14, 2006
    Assignee: GlobespanVirata Incorporated
    Inventor: Vasudev S. Nayak
  • Patent number: 7010025
    Abstract: An improved analog front end and methods for increasing the power efficiency of duplex signals on a transmission line are disclosed. The improved analog front end bifurcates a hybrid into a fixed portion and an adaptive portion. The adaptive portion combines a biquad and a summer to produce a filter transfer function suited to compensate for transmission line irregularities. A method for configuring a local transceiver to minimize power requirements at a remote transmitter is disclosed. Broadly the method entails, applying a transmit signal to a front end in the absence of a remote signal; optimizing the transmit signal power; recording the reflected transmit signal; applying an adaptive filter in response to transmission line irregularities; and controllably adjusting the adaptive filter to minimize the amplitude of the reflected version of the transmit signal in the receive path. A method for recovering a remotely generated signal is also disclosed.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: March 7, 2006
    Assignee: GlobespanVirata, Inc.
    Inventors: Markus Helfenstein, Drahoslav Lim, George S. Moschytz, Arnold Muralt
  • Patent number: 6999504
    Abstract: A method and apparatus are disclosed for reducing crosstalk in a telecommunication system. Broadly, the present invention utilizes a common mode signal to obtain additional information that can be used to better approximate the transmitted signal (by approximating and canceling crosstalk or otherwise). In accordance with one embodiment of the invention, a modem is provided having improved crosstalk cancellation circuitry for canceling crosstalk received on a local loop (or otherwise estimating the remotely transmitted signal) carrying modem communications. The modem includes a first input for receiving a signal carried on the local loop and a second input for receiving a signal obtained from the common mode. The modem further includes processing circuitry configured to either reduce crosstalk present in the signal carried on the local loop, or to otherwise closely approximate the remotely transmitted signal.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: February 14, 2006
    Assignee: GlobespanVirata, Inc.
    Inventors: Daniel Amrany, Patrick Duvaut, William Keasler, Laurent Pierrugues
  • Patent number: 6971057
    Abstract: A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 29, 2005
    Assignee: GlobespanVirata, Inc.
    Inventors: Marc Delvaux, Wenwei Pan, Jian Wang
  • Patent number: 6967996
    Abstract: An improved ADSL modem is presented. The ADSL modem in cooperation with a remote ADSL modem will exchange manufacturer identification information during initial DSL system training to establish a DSL communication link. The improved ADSL modem may comprise a memory device containing system parameters and operational algorithms previously determined to maximize DSL link performance between ADSL modems manufactured by different vendors. The improved ADSL modem is well suited for central office applications as it provides a solution for optimizing system performance that is transparent to remotely located ADSL modems. An ADSL modem in accordance with the present invention may comprise a digital signal processor and a memory device configured to store appropriate system parameters and operational algorithms that provide an optimized DSL communication link once applied during system initialization. The present invention also provides a method for optimizing DSL system performance.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: November 22, 2005
    Assignee: Globespanvirata, Inc.
    Inventors: Lujing Cai, Ehud Langberg, Shareq Rahman, William H. Scholtz
  • Patent number: 6961779
    Abstract: A system and method is provided for facilitating robust reception of multiple frame protocol messages. Initially, a first frame of data is received including therein a first segment of a multi-frame protocol message. Next, the received frame is placed into a data buffer. The buffer is then examined and the message contained therein is parsed to determine whether the received message is a complete message or not. If it is determined that the received message contained in the buffer is an incomplete message, a continuation message is sent to the remote transceiver ATU. However, if the message is determined to be complete, the message is parsed again and the complete message information contained therein is extracted and processed in accordance with the handshaking requirements. Upon receipt of the next frame in the message, this frame is concatenated onto the existing frames in the data buffer. The entire buffer is then re-parsed to determine its completeness.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: November 1, 2005
    Assignee: Globespanvirata, Incorporated
    Inventor: Herbert Lyvirn Lacey, III
  • Patent number: 6956872
    Abstract: The present invention is generally directed to a system and method for encoding a DSL information bit stream and decoding a corresponding encoded DSL symbol. In accordance with one embodiment, an apparatus for encoding a DSL information bit stream is provided having a switch with an input configured to receive a DSL information bit stream and at least two outputs. An encoder is provided and coupled to a first output of the switch. A serial to parallel converter is provided and coupled to both an output of the encoder and a second output of the switch. Finally, a mapper is provided and coupled to an output of the serial to parallel converter through multiple paths. Preferably, a first coupling path between the serial to parallel converter and the mapper is a direct path and a second coupling path includes a second encoder.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: October 18, 2005
    Assignee: GlobespanVirata, Inc.
    Inventors: Igor Djokovic, Patrick Duvaut, Massimo Sorbara
  • Patent number: 6952430
    Abstract: A system and method is provided for interfacing a protocol component with a physical layer component. Initially, a parameter setting message is sent to the physical layer indicating at least the mode of the processor. If the mode is nonframing, a handshaking tone or pattern detection request message is sent to the physical layer component enabling detection of specific handshaking tones or patterns. Next, a handshaking tone or pattern detection indicate message is received from the physical layer component indicating that a recognized tone or bit pattern has been detected in response to a detection request message. A signal request message is sent from the handshaking component to the physical layer component indicating that a handshaking message is to be transmitted as well as the content of that message. In addition, the signal request message also preferably includes parameters relating to the duration of the signal to be transmitted, such as a maximum and minimum symbol number.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 4, 2005
    Assignee: Globespanvirata Incorporated
    Inventor: Herbert Lyvirn Lacey, III
  • Patent number: 6952458
    Abstract: A demapping system and method for demapping symbols into bits, is provided. An embodiment of the system comprises a processor, and a memory that is coupled to the processor. The memory comprises a memory module that comprises a program that finds a hard demapper output d based on a received symbol r; finds a challenger ci for each i, the challenger ci is a challenger of the hard demapper output d, i is an integer whose maximum value is a number of bits of the challenger ci; calculates reliability mi for each i, the reliability mi is the reliability of the hard demapper output d; and calculates soft bit xi for each i, the soft bit xi is calculated based on the reliability mi.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: October 4, 2005
    Assignee: GlobespanVirata, Inc.
    Inventors: Igor Djokovich, Patrick Duvaut, Massimo Sorbara
  • Patent number: 6931343
    Abstract: An on-signal calibration system I and Q signals of a transmitter to remove distortions in the RF output signal. The transmitter generates I and Q values and converts, modulates and combines the I and Q values into the RF output signal for transmission. The calibration system includes a detector, a sampler, a selector, an imbalance estimator, and an IQ corrector. The detector senses the RF output signal and provides a detection signal indicative thereof. The sampler samples the detection signal and provides digital samples. The selector selects from among the digital samples that correspond to predetermined ranges of the I and Q values, or otherwise predetermined selection boxes at predetermined phases. The imbalance estimator determines at least one imbalance estimate based on selected digital samples. The IQ corrector corrects the I and Q values using at least one imbalance estimate.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: August 16, 2005
    Assignee: Globespanvirata, Incorporated
    Inventors: Mark A. Webster, Michael J. Seals, Bruce A. Cochran
  • Patent number: 6922444
    Abstract: A system and method for providing adaptive rate selection mitigates impulse-like noise and allows for interleaving and RS coding, while not excessively delaying data transmission. Generally, the system utilizes a memory and a processor, wherein the processor is programmed by software stored within the memory to perform the step of reading a specified data transmission delay rate for a channel utilized for data transmission. A Reed Solomon encoder is utilized by the adaptive rate system, which performs the steps of: reading a specified number of redundant bytes in a Reed Solomon frame; determining a level of impulse protection control from the number of redundant bytes in the Reed Solomon frame and a maximum code word length; and determining a number of symbols comprised within the Reed Solomon frame. In addition, an interlever is utilized for determining an interlever depth via use of said number of symbols comprised within the Reed Solomon frame and the specified data transmission delay rate for the channel.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: July 26, 2005
    Assignee: GlobespanVirata, Inc.
    Inventors: Lujing Cai, Danielle Liu
  • Publication number: 20050135305
    Abstract: Disclosed herein are exemplary techniques for initiating a direct wireless link between two wireless devices. The method includes transmitting, a first frame from a first wireless device having a destination media access control (MAC) address; receiving, at the first wireless device, a second frame from a second wireless device, the second frame having a destination MAC address and being intended for a wireless device other than the first wireless device; and establishing a direct wireless link between the first wireless device and the second wireless device when the when the destination MAC address of the first frame matches the destination MAC address of the second frame.
    Type: Application
    Filed: November 1, 2004
    Publication date: June 23, 2005
    Applicant: GlobespanVirata, Inc.
    Inventor: Menzo Wentink
  • Publication number: 20050135304
    Abstract: Disclosed herein are exemplary techniques for initiating a direct wireless link between two wireless devices.
    Type: Application
    Filed: November 1, 2004
    Publication date: June 23, 2005
    Applicant: GlobespanVirata, Inc.
    Inventors: Menzo Wentink, Arnoud Zwemmer
  • Patent number: 6909781
    Abstract: An analog front end system comprising a digital-to-analog converter, a line driver, a multiple-input device, and an analog-to-digital converter is presented. Furthermore, a method for DSL line testing comprising the steps of providing test stimuli to and receiving responses from a DSL line using an analog front end is presented. The presented system and method provides for the testing of a DSL line in an xDSL communications system deployment.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: June 21, 2005
    Assignee: GlobespanVirata, Inc.
    Inventor: Benedict A. Itri
  • Publication number: 20050130634
    Abstract: Disclosed herein are exemplary techniques for establishing a direct link independent of an access point and for identifying proximate wireless stations users. The method and method are provided in a wireless network with an access point logically connected to at least a first wireless device and a second wireless device to notify the first wireless device that the second wireless device is in proximity to said first device. The system and method also establish a direct wireless link between a first wireless device and at least one proximate wireless device by identifying a second wireless device within a predetermined proximity of the first wireless device, determining an identity associated with a user of the second wireless device, comparing the identify with a set identities, and notifying the user of a proximity of the user of the second wireless device based on the comparison.
    Type: Application
    Filed: November 1, 2004
    Publication date: June 16, 2005
    Applicant: GlobespanVirata, Inc.
    Inventor: Timothy Godfrey
  • Patent number: 6894580
    Abstract: A system and method for a filter tuner is presented. The system comprises a sequential logic, a register, a comparator, a first and second counter, a synchronizing logic, a first and second oscillator, a control logic, and a first and second combinational logic. The method comprises the steps of executing a calibration cycle of a filter tuner, executing a measurement cycle of the filter tuner, and tuning a filter with the filter tuner dependent on a determined cutoff frequency variation.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 17, 2005
    Assignee: GlobespanVirata, Inc
    Inventors: Brian Horng, Benedict A. Itri, Devin Ng, John Ross, James J. Zhao
  • Patent number: 6879625
    Abstract: A system and method for providing cancellation of interference in a repeater configuration is disclosed, wherein the repeater is located between a first endpoint and a second endpoint. A data signal received from the first end point is amplified in accordance with an amount of power required to drive the data signal to the second endpoint. Local echo introduced by the repeater is then removed from the amplified data signal. Coupled signals introduced by the repeater are then removed after which the data signal is transmitted to the second endpoint.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: April 12, 2005
    Assignee: GlobespanVirata, Inc
    Inventors: Robin Levonas, Ehud Langberg
  • Patent number: 6856953
    Abstract: The present invention relates to an algorithm for ensuring compliancy of an algorithm module when integrated in a real time software system. The compliancy tests may include a memory test, interrupt test, latency test and other tests, as well as combinations thereof. An inventive aspect of the present invention relates to a unit test harness for verifying that a software algorithm module meets performance and functional requirements when integrated in a complete real-time software system. A software algorithm module eliminates or reduces unwanted behavior by the caller or other software on a real-time software system due to incorrect operations, which may involve interrupts, memory usage, register usage and/or other factors.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: February 15, 2005
    Assignee: GlobespanVirata, Inc.
    Inventors: Matthew Randmaa, Murali Anantha, David Lindsay, Keith Dillon
  • Patent number: 6854025
    Abstract: A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: February 8, 2005
    Assignee: GlobespanVirata Incorporated
    Inventors: Brian Knight, David Milway