Abstract: A method and a system for using a network switch, such as in a gateway, to route frames between network segments are disclosed. Frames from one network segment can be provided to one of a plurality of ports of a network switch. The network switch provides the frames to a processor, whereupon the processor performs any higher-level processing of the frames, such as Internet Protocol Security (IPSec) or network address translation (NAT). After any applicable modification of the frame the processor provides the modified frame back to the network switch for output on a port associated with a network segment that includes the intended destination of the frame.

Abstract: The present invention is directed to a system and method for minimizing signal distortion in a discrete multi-tone communications system that is being used in both the POTS and the ADSL frequency bands. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to insert a probe signal into the upstream channels of the communication system, measure the resulting signal distortion in the downstream channels, and adjust the upstream signal power to minimize system signal distortion due to the upstream data transmission. The system and method further estimates the POTS band signal distortion based on the measured distortion at the higher frequencies, and adjusts the output signal power at the central office equipment to minimize signal distortion at the customer premises.

Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: A system and method is provided for enabling analysis of memory buffer usage. Initially, each of the buffer using system components are assigned a unique ownership tag. Next, upon buffer allocation to a particular component, the allocated buffer is tagged with the calling component's ownership tag. Once tagged, the system operates conventionally, with the calling component utilizing the buffer to perform any task it has been assigned. Following completion of its tasks(s), the calling component calls a buffer checker application which searches the buffer pool for the calling component's ownership tag. Next, upon search completion, the calling component determines whether the buffer checker has identified the calling component's ownership tag in its search. If so, a potential buffer leak is identified and a log of such occurrences is created. A system developer or administrator then periodically reviews the log for potential buffer leakage occurrences to assist is subsequent debugging and analysis.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: A combined cable/digital subscriber line (DSL) modem and method for data transmission. Upstream data is transmitted to a data communications network through a two wire pair to a central office using unidirectional DSL transmission. Downstream data is transmitted from the data communications network to the combined cable/DSL modem via a cable network using unidirectional cable transmission. Thus, bi-directional data communications is established using two unidirectional transmission links for faster and more efficient data communication.

Abstract: A method and system to minimize the potential of jitter buffer underflow/overflow resulting from a difference in sampling rates of an audio encoder and an audio decoder are disclosed herein. The difference in sampling rates, or clock skew, can be determined from a difference between an actual amount of data stored in a jitter buffer and the desired, or threshold, amount. A subset of packets from a sequence of packets output to the audio decoder can be altered to compensate for the clock skew, whereby the amount of data associated with the subset of packets is decreased when the sampling rate of the encoder is greater than the sampling rate of the decoder, and the amount of data is increased when the sampling rate of the encoder is less than the sampling rate of the decoder. The present invention finds particular advantage in providing audio data via a packet-switched network.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: A system and method is presented for dividing a reference clock frequency by any real number. The invention allows for a real number divisor that could have any desired degree of precision. Additionally, the invention seeks to minimize hardware complexity in realizing such a reference-clock frequency divider. In one particular embodiment of the invention, a system and method is presented, wherein the real number divisor is a real number having a repeating decimal (i.e., the real number may be represented by a fraction).

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: A system and method for providing a virtual Point-to-Point Protocol over Ethernet (PPPoE) session between a client unable to support a PPPoE session and an access concentrator are disclosed herein. A gateway situated between the client and the access concentrator can act as a proxy PPPoE client between the client and the access concentrator, thereby allowing the client to send and receive data to/from the gateway in a protocol supported by the client, and the gateway provides this data to the access concentrator through a PPPoE session initiated and maintained by the gateway. Likewise, data from the access concentrator to the client is transmitted through the PPPoE session to the gateway, and the gateway reformats the data using a protocol supported by the client and then forwards the reformatted data to the client.

Abstract: A processing circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a data pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: A SINC filter for an oversampling Sigma-Delta digital to analog converter (OSDAC) having a cascaded construction that results in reduced sensitivity to capacitor mismatch. Specifically, the SINC filter circuit filter may be defined by a transfer function H(z), which is further defined by first constituent transfer functions H1(z) and H2(z). The constituent transfer functions may be implemented in a cascaded fashion. Preferably, one of the cascaded sections includes a resistor string that defines a plurality of reference voltages. A plurality of switching elements are configured to controllably switch these reference voltages to a capacitor of a tap.