Abstract: A system and method for performing a general ternary branch instruction is provided. Additionally, different approaches are provided for reducing the complexity of a ternary branch instruction word and corresponding hardware.

Abstract: A radar detector (10) includes a first period detector (76, 122), a second period detector (96, 120) and a third period detector (86, 124) within a multi-period periodicity validator 38. The first period detector (76, 122) detects radar pulses exhibiting one-half of an expected pulse period (48), the second period detector (96, 120) detects radar pulses exhibiting the expected pulse period (48), and the third period detector (86, 124) detects radar pulses exhibiting twice the expected pulse period (48). A plurality of pulse-train records (40) can simultaneously track a plurality of possible pulse trains. A control element (84, 136, 138) accounts for missing pulses and corrects the expected pulse period when missing pulses have caused the expected pulse period to be inaccurate.

Abstract: Systems and methods for increasing data capacity in communication systems is presented. In one embodiment, line characteristics are determined, and a downstream bandwidth is adaptively allocated in response to the determined line characteristics. In this regard, the upstream and downstream bandwidths may be seen as adaptively changing as a function of line characteristics.

Abstract: A “Smart DSL System” for addressing the performance objectives of LDSL and examples of smart systems for LDSL are disclosed. In accordance with embodiments of the invention, there is disclosed a method for implementing smart DSL for LDSL systems. Embodiments of the method include presenting a number of spectral masks that are available on the LDSL system, and selecting from the number of spectral masks an upstream mask and a downstream mask wherein the upstream mask and the downstream mask exhibit complimentary features.

Abstract: A system and method for reducing transmit carrier wander in a DSL communication system are disclosed. A network timing reference unit provides an automatic embedded solution for synchronizing DSL frames to an external communication system reference clock. The network timing reference unit applies or removes bits to adjust the length of a DSL frame in response to a sliding window state table. A sliding window is selected in response to the relative position of the DSL frame to a system clock reference point over a number of DSL frames. A network timing reference unit in accordance with the present invention may comprise a counter, a network timing latch, a synchronization word detector, a DSL frame latch, a lead/lag comparator, a sliding window buffer, a sliding window state table, a DSL frame state recorder, and a sensitivity buffer. The present invention provides a method for reducing transmit carrier wander in a DSL transceiver.

Abstract: A radar detector (10) includes a first period detector (76, 122), a second period detector (96, 120) and a third period detector (86, 124) within a multi-period periodicity validator 38. The first period detector (76, 122) detects radar pulses exhibiting one-half of an expected pulse period (48), the second period detector (96, 120) detects radar pulses exhibiting the expected pulse period (48), and the third period detector (86, 124) detects radar pulses exhibiting twice the expected pulse period (48). A plurality of pulse-train records (40) can simultaneously track a plurality of possible pulse trains. A control element (84, 136, 138) accounts for missing pulses and corrects the expected pulse period when missing pulses have caused the expected pulse period to be inaccurate.

Abstract: An improvement to system clock synchronization corrector in a digital transceiver allows the generation of a phase error correction signal for use in an imbedded clock synchronization control loop without the use of additional transmitted information or additional external circuitry. The system allows a transceiver to achieve timing and synchronization lock to a system master clock, such as a T1 or E1 clock, by triggering a counter to supply a count responsive to a higher-frequency replica of the local clock signal with the network clock signal. A network timing reference unit generates a phase error offset by clocking data into comparison registers in response to the maximum counter values. Subsequent counter values are mathematically combined to generate a series of phase offset samples. The phase error samples may be stored and or further manipulated to generate a phase error correction signal for use in a clock synchronization control loop.

Abstract: An improved line driver-hybrid and method for increasing the power efficiency, signal accuracy, and stability of a transmit signal on a transmission line are disclosed. The improved line driver-hybrid uses a negative feedback control loop, thereby enhancing operational stability and suppressing both amplifier imperfections and discrete component manufacturing variances. Furthermore, the improved line driver-hybrid provides a power efficient full duplex solution for line driver applications. The present invention can also be viewed as providing a method for actively terminating a transmission line.

Abstract: There is provided a method and system for facilitating the allocation and management of system resource modules. Applications request services directly from a controlling library rather than directly from the resource. Initially, system service providers register capabilities and relative priorities with the controlling library. Following registration, the controlling library will receive all service requests from applications. In response, the controlling library identifies the available resource having the highest priority and passes the service request to that resource.

Abstract: An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.

Abstract: A system and method for modifying the spectrum allocation for DSL and LAN signals in accordance with bandwidth requirements of a small office, home office (SOHO) network is disclosed. After initiation of computers within the SOHO network, a handshake procedure is performed between the SOHO network and a wide area network (WAN). The handshake procedure discloses bandwidth requirements for the SOHO network to perform local communication between local area networks (LANs), and for the SOHO network to communicate with the WAN. As a result, the system modifies the spectrum allocation for digital subscriber line (DSL) and LAN signals associated with the SOHO network such that maximum bandwidth allocation is provided in accordance with actual bandwidth need.

Abstract: A multi-channel communication link generates a transport data protocol unit (TPDU) corresponding to each data packet received at a particular interface in a packet switching network. Each TPDU may comprise a data packet in accordance with a standard data transfer protocol and a modified header comprising a sequence number responsive to the relative position of the data packet within a data stream. The multi-channel communication link may inverse multiplex the various TPDUs for transmission across a plurality of asynchronous communication lines. A multi-channel communication link in accordance with the present disclosure may comprise a source first-in first-out (FIFO) buffer, a source line multiplexer/demultiplexer, a plurality of asynchronous communication links, a destination line multiplexer/demultiplexer, and a destination FIFO buffer. The present disclosure also provides a method for transferring data between computing devices via a virtual transport link.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: A system and a method for constructing a signal integrity supervisor capable of both detecting and triggering an appropriate response when transmit path signals indicate a potential damaging transmitter operating mode. The system and method of the present invention takes advantage of the inherent property of a Delta-Sigma Modulator (DSM) which makes the probability of encountering a long string of consecutive ones or zeroes during nominal operation very small. The signal integrity supervisor ensures safe transmitter operation by monitoring the data and the clock inputs to a digital to analog converter. The system may comprise a data signal supervisor and a clock signal supervisor. The data supervisor may comprise a comparator and a counter and may be configured to power down a line driver upon detecting a data stream having a continuous voltage level.

Abstract: Mechanisms for providing a subscriber-side interface with a passive optical network are described herein. An optical network termination (ONT) having an integrated broadband passive optical network processor is utilized to receive downstream data from an optical line termination (OLT) via a passive optical network and provide the contents of the downstream data to one or more subscriber devices via one or more data interfaces. Similarly, the ONT is adapted to receive and transmit upstream data from the one or more subscriber devices to the OLT via the passive optical network. The ONT preferably implements one or more encryption/decryption mechanisms, such as the digital encryption standard (DES), to provide data protection in addition to, or in place of, data churning provided for by the ITU G.983 recommendations.

Abstract: The present invention is directed to a signal processing and amplifying system that uses advance knowledge of a digital signal, before it is converted to analog form and applied to the input stage of the amplifier stage, to “intelligently” amplify the signal with the maximum power efficiency and minimal distortion. This advance knowledge of the digital signal allows a switch control logic (SCL) unit to open and close solid state switches and seamlessly turn off and on the low and high power stages correctly to minimize the amplifier distortion while conserving power. In one embodiment, the system comprises a shift register, which receives the supplied digital signal to be amplified and delays the digital signal by a known amount, a digital to analog converter, an amplifying circuit, which is made up of at least two amplifiers, and an SCL unit. The SCL unit comprises control logic, and multiple solid state switches.

Abstract: The present invention is directed to a system and method for determining when a particular tone in a discrete multi-tone communications system is being used to transmit a control signal. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to detect a constant phase shift on individual tones when a control signal condition is present.

Abstract: Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a plurality of ribs. The shield layer is formed a select distance from the conductive turns. The shield layer is patterned into sections of shield to prevent eddy currents. The plurality of ribs are formed from a conductive layer that is positioned between the conductive turns and shield layer. Each rib is electrically coupled to a single associated section of shield. Moreover, each rib is more conductive than its associated section of shield to provide a less resistive current path than its associated section of shield.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase without increasing the maximum current in the line driver output stage. The output stage of the line driver may comprise a first amplifier, a second amplifier, and an integrated back-matching resistor network. In order to further increase the available transmit power; a protective semiconductor device may be added to a line driver output stage for each semiconductor device in the first and second amplifiers. A third embodiment of a line driver output stage in accordance with the present invention may comprise a combination of the integrated back-matching resistor network along with the protective semiconductor devices.

Abstract: In accordance with one aspect of the invention, an apparatus is provided having a transmit path and a receive path for communicating data. The apparatus includes an analog to digital (A/D) converter that is disposed in communication with the receive path. The A/D converter operates at a first sampling rate, and it converts a received analog signal into a digital signal. The apparatus also includes a first echo canceller that is in communication with the receive path and that operates at the first sampling rate for estimating a first portion of an echo signal leaking from the transmit path to the receive path. The estimated echo signal is subtracted from the digital signal. The amplitude of the digital signal is increased by a digital gain. A decimator is disposed in communication with the receive path, whereby the decimator filters the digital signal that has a first sampling rate and emits a signal output at a reduced sampling rate.