Abstract: A one-wire protocol is described, wherein a one-wire bus has either a wired-AND configuration or a wired-OR configuration. In this protocol, data is encoded using time modulation. In one embodiment, two devices communicate with each other through the one-wire bus. One device is configured to transmit data by driving the one-wire bus high, while the other device is configured to transmit data by driving the one-wire bus low. In a preferred embodiment, transmission of data by each of the two devices is interleaved in such a fashion so that there is a bit-for-bit exchange between one device and the other device. In another embodiment, more than two devices may communicate through the one-wire bus.

Abstract: In accordance with one aspect of the invention, an apparatus is provided for facilitating combined xDSL and POTS communication across a two wire pair. The apparatus includes a first communication port for communication with a central office across a two wire pair, and a second communication port for communication with a customer premises across a two wire pair. A splitter, or tap, is disposed at the first communication port for splitting a combined xDSL and POTS signal into a first and second signal path. A low pass filter is disposed in the first signal path for filtering the xDSL signal from the combined signal in the first signal path, leaving only the low-frequency (POTS frequency) signals. A circuit is disposed in the second signal path that is configured to filter the POTS signal from the combined signal, leaving only the xDSL signal.

Abstract: Disclosed herein are a method and system for sharing a single GPIO line of an integrated circuit (IC) between at least two circuit components connected concurrently, wherein at least one of the circuit components is to provide input via the GPIO line and at least one circuit component is to receive output via the GPIO line. The input and output can be provided at separate times with the status of the GPIO line changing accordingly or, provided that the input is provided at a lower frequency relative to the switching frequency of the GPIO line, an input to the IC can be provided concurrent with an output from the IC since the low frequency input typically persists until an input cycle of the GPIO line. The present invention finds particular benefit when implemented to interface with GPIO lines of a microprocessor.

Abstract: A system and method for performing peak-to-average power ratio reduction in a transmitter using pulse amplitude modulation (PAM) encoding. Broadly, a transmitter is configured to perform active digital filtering to detect encoded data symbols that if uncorrected would lead to relatively high analog signal peaks in the data transmission. A prediction is made of the peak values that would be applied at the digital to analog converter (DAC) if the original output of the Tomlinson precoder was sent into the shaping filter. If the absolute value of the predicted peak value exceeds a threshold, a correction of a full 2L step is applied for one sample of the Tomlinson precoded stream. The correction step is applied in such a way as to reduce the resulting peak output. Two methods of predicting the peak values are presented. The first method segments the shaping filter into causal and non causal portions so that no extra delay is introduced.

Abstract: A system and method for facilitating the scheduling and transmission of transmit protocol messages. Initially, a write credit count is maintained indicating the number of write credits available to a transmit message processor. Upon receipt of a data frame for transmission to a data pump, the transmit message processor determines whether the write credit count is greater than 0. Of so, the frame is dequeued and the message is sent to the data pump for transmission on the wire to a receiving peer end. However, if the write credit count is 0, a waiting_for_write_credit flag is set to true indicating that the transmit processor has a frame waiting for transmission, but lacks sufficient write credits to send the frame to the data pump. Once an additional write credit is received from the data pump, the write credit count is incremented and the waiting_for_write_credit flag is checked to see if any frames are waiting to be send.

Abstract: A system and method for filter tuning are presented. The system comprises means for adjusting the components of a filter by coarse adjustments such that the filter is set with an initial cutoff frequency of adequate accuracy to satisfy the requirements of the filter application, and means for adjusting the components of the filter by fine adjustments such that the filter is set to maintain the accuracy of the initial cutoff frequency in response to cutoff frequency drift. The method comprises the steps of adjusting the components of a filter by coarse adjustments such that the filter is set with an initial cutoff frequency of adequate accuracy to satisfy the requirements of the filter application, and adjusting the components of the filter by fine adjustments such that the filter is set to maintain the accuracy of the initial cutoff frequency in response to cutoff frequency drift.

Abstract: A system and method is provided for interfacing a protocol component with a physical layer component. Initially, a parameter setting message is sent to the physical layer indicating at least the mode of the processor. If the mode is nonframing, a handshaking tone or pattern detection request message is sent to the physical layer component enabling detection of specific handshaking tones or patterns. Next, a handshaking tone or pattern detection indicate message is received from the physical layer component indicating that a recognized tone or bit pattern has been detected in response to a detection request message. A signal request message is sent from the handshaking component to the physical layer component indicating that a handshaking message is to be transmitted as well as the content of that message. In addition, the signal request message also preferably includes parameters relating to the duration of the signal to be transmitted, such as a maximum and minimum symbol number.

Abstract: A system and method is provided for reliably filtering out data frames from a line trace, wherein the frames include variable, vendor specific idle pattern bytes. Initially, a idle pattern buffer is filled with the default idle pattern. When the protocol identifies an actual received idle pattern, the content of the idle pattern buffer is replaced with the identified idle pattern. Subsequent receive buffers are compared to the idle pattern buffer, and only those received buffers that do not match (i.e. contain at least one bit different from the idle pattern buffer) are included within the line trace.

Abstract: A system and method is provided for integrating the functionality of an interface to a power management driver for a communications system and the communications protocol which negotiates power management transitions. Initially, a driver power management request is received at the UPI component. In response, the UPI component, determines whether a port is open on which to send the state transition request. If it is determined that a port is open, it is next determined whether a suitable power management protocol is available. If it is determined that a port is open and the power management protocol is available, the UPI sends a power management state transition request through the EOC to the remote modem. Next, it is determined whether the remote modem has responded.

Abstract: A system and method for determining fault path behavior in a computer software system. An error or event, the occurrence of which is to be tested, is assigned a probability value and an array of elements populated by pseudo-random numbers. Upon each operation of the system under test the current array value is compared against the probability value. If the current array value is greater than or equal than the probability value, the error or event is simulated within the software. Otherwise, the event is not simulated and the software is left to operate conventionally. The array is incremented upon each occurrence of the system under test.

Abstract: A system and method is provided for uniquely handling exception an interrupts in at least two different processors in a multiprocessor system. Initially, the memory address identified in a common exception vector table is written to contain an instruction which copies the current version of an IRQ-mode banked register into the program counter of the processor for subsequent execution. Next, each processor initializes independent IRQ-mode registers to contain the respective addresses for their individual IRQ handler routines. Upon receipt of an interrupt request or other exception, the processor receiving the request changes to an IRQ-mode, resulting in at least one register change from a normal register to the previously initialized IRQ-mode register. Next, the processor looks in the exception vector table for the appropriate interrupt handler address location and jumps to the identified memory location.

Abstract: A system and method is provided for facilitating robust reception of multiple frame protocol messages. Initially, a first frame of data is received including therein a first segment of a multi-frame protocol message. Next, the received frame is placed into a data buffer. The buffer is then examined and the message contained therein is parsed to determine whether the received message is a complete message or not. If it is determined that the received message contained in the buffer is an incomplete message, a continuation message is sent to the remote transceiver ATU. However, if the message is determined to be complete, the message is parsed again and the complete message information contained therein is extracted and processed in accordance with the handshaking requirements. Upon receipt of the next frame in the message, this frame is concatenated onto the existing frames in the data buffer. The entire buffer is then re-parsed to determine its completeness.

Abstract: The present invention is directed to a system and method that efficiently, accurately, and quickly detects a suitable stored fast retrain profile to permit the resumption of ADSL communications in the presence of changing line conditions in a dual POTS/ADSL communications system. The method of the present invention is based on measuring the amplitude and phase of a few discrete multi-tone tones in the receiver portion of a communications system and recording the number of times a profile is selected to replace a preceding profile. Broadly, the system and method of the present invention are realized by a digital signal processor that is configured to detect a fast retrain request, select a suitable stored profile, and apply the parameters associated with the selected profile to configure the customer premises modem.

Abstract: A system and method for providing additional voltage to an amplifier circuit, wherein the voltage is supplied using a single voltage supply and the amplifier voltage rail is configured to track the amplitude of the input signal.

Abstract: A continuous-time smoothing filter circuit and method for implementing the same are disclosed. The circuit may be implemented as a cascade of two sections. The first section may comprise two programmable 3rd order low-pass filters, each filter having a low Q value complex pole pair, as well as, a negative real pole. The second section may comprise an output stage amplifier having a low output impedance in order to drive external loads. Each of the 3rd order low-pass filters may be under programmable control to select and coarsely tune the cut-off frequency for each of the two filters. In its broadest terms, the method of the present invention can be described as: processing a digital to analog converter generated output signal with a first 3rd order low-pass filter; processing a first output signal provided by the first 3rd order low-pass filter with a second 3rd order low-pass filter; and processing a second output signal provided by the second 3rd order low-pass filter with a low-output impedance amplifier.

Abstract: The present invention is directed to a system and method for reducing the need to perform signal clipping in a DMT transmitter. In accordance with one aspect of the invention, a method performs an inverse Fourier Transform on the input to produce a time-domain, digital value to be transmitted to a remote receiver. The method then evaluates the magnitude of the digital value to determine whether the magnitude exceeds a threshold value. Then, the method alters the input and re-performs an inverse Fourier Transform on the altered input, only if the step of evaluating the magnitude determines that the magnitude of the digital value exceeds the threshold value.

Abstract: An ADSL system for operating in a time duplex system that provides alternative configurations for limiting crosstalk in a broadband network is disclosed. The ADSL system introduces a trial bitmap profile configuration to maximize the bit rate at which information is transmitted, regardless of network topology. In a simplified embodiment, a composite signal to noise ratio is derived from a minimum far end crosstalk signal to noise ratio and a minimum near end crosstalk signal to noise ratio. A maximum bit rate for the transfer of information, which is directly related to the derived composite SNR, is then determined. Information is then transmitted simultaneously between an asymmetric digital subscriber line central office and an asymmetric digital subscriber line customer premise at the determined maximum bit rate.

Abstract: An improved method and apparatus for active line termination is disclosed. An active termination line driver (ATLD) includes a pair of power amplifiers configured to amplify a transmit signal, the amplifiers comprise a first input for receiving the transmit signal, a second input for receiving a feedback signal, and an output configured to provide the amplified transmit signal to the load. The ATLD also includes a resistive network configured to provide the feedback signal from the outputs of the amplifiers to the second inputs power amplifiers. The resistive network is selectively configured to facilitate any one of a plurality of feedback configurations to emulate a back-matching impedance. Other embodiments of the present invention may be construed as methods for power efficiently driving a transmit signal to a load.

Abstract: In general, the line driver is defined by an input and output stage wherein the input stage is identified by the deriving of the open loop gain of a preamplifier and the output stage is defined by the deriving of the open loop gain of two drivers that provide power required for the line driver to drive a line. Both, the preamplifier and the drivers have inputs that sit at a common mode voltage, thereby inhibiting a common mode input voltage swing and limiting distortion in the line driver. The gain of the preamplifier may be changed to a desired value by regulating the values of resistors therein, thereby reducing distortion by maximizing the open loop gain for all lines and DSL applications. The line driver can be configured for any desired closed loop gain, regardless of whether the gain value is below or above 1. The drivers of the, output stage use a set of programmable output devices to allow for maximum drive capability of the drivers to be programmed under digital control.

Abstract: The present invention is generally directed to a processing circuit for computing a fast Fourier transform (FFT). The present invention reflects the recognition that excessive reads to and writes from memory consume excessive amounts of power. Accordingly, the circuit of the present is specifically designed to minimize the number of reads and writes to memory. In addition, the circuit is designed so that processing parallelism may be achieved in order to reduce the total number of clock cycles required to compute a FFT. In accordance with one aspect of the invention, the processing circuit includes a data memory for storing data values, and a separate coefficient memory for storing coefficient (or twiddle) values. The circuit further includes a multiplier configured to multiply values received from the coefficient memory and another value retrieved from some other location.