Abstract: Devices and method for effectively filtering a signal, particularly for a communication system, are disclosed. In this regard, an exemplary embodiment of the present invention may be construed as an AFE that includes a high-pass receive filter for a communication system. The filter includes an AC-coupled capacitive input and a plurality of RC integrators. At least one of the plurality of RC integrators includes a damping resistor in parallel with a feedback capacitor and a switch for enabling the damping resistor, such that when the damping resistor is enabled, the at least one RC integrator is damped so as to reduce DC instability.

Abstract: A system and method to perform partial byte writes in a processor circuit is disclosed. The system comprises a bit assembly circuit having a bit assembly register with a corresponding shadow register. Also included is a bit routing circuit configured to transfer at least one data bit from a data bus to a predetermined register position in the bit assembly register and a shadow bit from the data bus to a corresponding register position in the shadow register. The shadow bit indicates that the data bit written comprises valid data. The bit assembly and shadow registers may receive data directly from the data bus as well. Using this circuitry, a partial parallel data block is assembled in the bit assembly register. Thereafter, the partial parallel data block is transferred to a destination register via the data bus with corresponding shadow bits being transmitted to the destination shadow register. The valid data is processed accordingly.

Abstract: A system, method, and apparatus are disclosed for minimizing the memory required by memory management structures in a multi-threaded operating environment. The shortest necessary lifetime of a memory management structure is determined to allow the memory required to maintain the memory management structure to be reallocated for other uses when the memory management structure is no longer required. A memory management structure comprises a synchronization object for each data segment. A link list of synchronization nodes is also maintained to identify to the read thread a next data segment to be read and comprises a segment ready indicator that also indicates whether a data segment is available for access. If the segment ready indicator indicates to the read thread that the data segment is available for access, the read thread proceeds directly to reading the data segment without accessing the synchronization object.

Abstract: An RF device including a control loop for maximizing output power for each of several data rates or constellation types. The RF device includes a power detector, a power amplifier and a MAC that includes input and output adjust circuits. A power level value is generated from measured output power. The MAC compares an adjusted power level value with a set point value and generates an error value. The MAC adjusts a power control value based on the error value for controlling the gain of the power amplifier. The MAC uses a data rate signal indicative of a selected constellation type or data rate. The input adjust circuit stores one or more input adjustment values selected by the data select signal for adjusting the power level value. The output adjust circuit stores one or more output adjustment values selected by the data select signal for adjusting the power control value.

Abstract: The present invention is directed to a system and method for upgrading a telecommunication system including a central office (CO), a digital loop carrier (DLC), and a plurality of customer premises equipment (CPE). Broadly, the present invention is realized by the retrofit of a DLC to enable the DLC to communicate with a CO through high bandwidth wireless transmissions. The high bandwidth wireless transmissions accommodate much larger data throughput than previously accommodated through the copper “backhaul” of multiple T1 circuits. In accordance with one aspect of the present invention, a telecommunications system comprises a CO, a DLC, and a plurality of CPE. Each of the plurality of CPE are electrically connected to the DLC. A radio frequency (RF) interface circuit is disposed at the DLC, along with one or more DSL line cards. A first wireless transceiver disposed at the DLC, and is electrically connected to the radio frequency interface circuit.

Abstract: An exemplary mechanism for intelligent Point-to-Point Protocol over Ethernet (PPPoE) initialization is disclosed herein. During the PPPoE discovery stage, a PPPoE client of a CPE determines the status of a connection between the CPE and an access concentrator prior to transmitting a PADI and/or PADR packet. If a physical layer connection is established, the PPPoE client can provide the packet to the physical interface for transmission to the access concentrator. If a physical layer connection is not established, the PPPoE client either periodically rechecks the status of the connection until a physical layer connection is established or the PPPoE can terminate the PPPoE discovery stage after a certain number of iterations. Additionally, prior to waiting for a PADO or PADS packet, the PPPoE client can be adapted to check the status of the connection. If a physical layer connection exists, the PPPoE client can initiate the wait for the packet.

Abstract: A data bus address extender is presented. The data bus extender may be deployed in cooperation with a master device to extend the number of addressable physical devices on a data bus without modifying the number of address bits used to identify the various slave devices on the bus. The data bus extender of the present invention can be used in existing data bus systems with minimal impact as it does not require a change at the slave devices. A data bus address extender in accordance with the present invention may comprise an address stripper and a range select decoder wherein at least one of the address bits at the slave side of the bus is enabled by the range select decoder. The present invention also provides a method for extending the number of addressable communication devices on a data bus.

Abstract: The present invention is directed to a system and method that detects periods of no activity in the downstream data path of a DSL modem and reduces the transmit power in the output line driver to reduce power consumption in the modem. A preferred method is operative at the central office DSL modem and comprises detecting periods of no activity in the downstream data bins, reducing the transmit power in response to the inactivity on the communication link, detecting either upstream or downstream data, and performing a fast retrain of the modem to restore nominal power data transmission in the downstream direction. A variation of the preferred method uses a reduced point constellation encoding scheme to reduce power consumption. Broadly, the system of the present invention may be realized by a configurable transmit channel line driver and a digital signal processor.

Abstract: A method and apparatus for encoding data bits in DMT modulation system is providing utilizing a 64-state Trellis encoder to achieve further improvement in the achievable coding gain by employing coset partitioning, bit conversion, and constellation encoder that fit the DMT modulation. The coding gain of the new coder is around 5.63 dB, which is about 0.96 dB higher than the current Trellis coder in the DMT standard.

Abstract: The present invention relates to improved ADC buffers and AFEs for high frequency applications, such as VDSL. The present invention can also be programmably configured for other xDSL applications. In this regard, a buffer circuit for a high-bandwidth analog-to-digital converter (ADC) includes a first unity-gain buffer configured to receive an analog input signal. The first unity-gain buffer includes a MOSFET differential amplifier with a current mirror load and a transient-reduction network electrically interconnected with the MOSFET differential amplifier and configured to reduce transient energy emitted by the ADC. The buffer circuit also includes a second unity-gain buffer cascaded to the first unity-gain buffer and configured to provide the analog input signal from the first unity-gain buffer to the ADC.

Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.

Abstract: The present invention is directed to a system and method for establishing a point to multipoint communication network. Preferable, the point to multipoint communication network is established in the environment of a home of small office, and the invention is realized through a computer that may dynamically establish both LAN and WAN communications. Broadly, the system and method of the present invention are realized by a computer that is configured to assume a role as either a Master or a Slave on a LAN. If the computer is the first (or only) computer powered up on the LAN, then it assumes the role of Master. In this role, the computer establishes a communication link with a WAN (such as with an Internet Service Provider), and directs all WAN communications over the WAN, using a WAN frequency and protocol (such as DSL). As other computers join the LAN, then WAN communications from those computers are relayed through the Master to the WAN.

Abstract: An adaptive filter for echo cancellation includes a segmented sparse transversal filter having an input, the filter having an adjustable length, adjustable lengths for the segments and adjustable tap weights. The adaptive filter further includes an adaptive tap weight control mechanism providing a tap weight vector including tap weights and a tap weight vector length to the taps of the transversal filter, the adaptive tap weight control mechanism setting the tap weights and the tap weight vector length in response to comparison of estimated truncation error to a target truncation value and in response to a magnitude of integrated cross correlation coefficients between a reference signal and an error signal from the adaptive filter.

Abstract: A system and method for formatting and transmitting DMT symbols. For each symbol to be transmitted, the last Lcp samples of the symbol are prepended to the symbol as a cyclic prefix. Next, of the samples contained within the cyclic prefix, the first Î2 samples are appended to the symbol as a cyclic suffix. By providing the above described cyclic prefix and suffix, sharp PSD transitions are provided in the first overlapped RFI band (1.8-2 MHz) and out of band PSD. Upon formatting, each symbol is transmitted so that its transmission overlaps the prior symbol by Î2 samples. This results in the output signal being shaped by a raised cosine function for the duration of the Î2 overlap.

Abstract: The present invention is directed to a computer system having novel circuitry for coupling peripheral cards to a power line network. In this regard, the computer includes a switching power supply having coupling circuitry for coupling an electrical signal with a power line, a filter circuit electrically connected to the coupling means for receiving an electrical signal from the coupling means and filtering the received signal, and an amplifier circuit electrically connected to the filter circuit for amplifying the filtered signal. The computer system also includes at least one peripheral circuit (e.g., PC card). An infrared transmitter is coupled to the amplifier circuit for transmitting an infrared signal. Finally, the computer includes an infrared receiver coupled to the peripheral circuit for receiving the scattered infrared signal. In accordance with another embodiment of the invention, a power line adapter is provided for communicating signals between a power line and a computer.

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract: The present invention is directed to an apparatus and system for selectively inhibiting access to a memory during a DMA block transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine's request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.

Abstract: A system and method for ADSL USB bandwidth negotiation are presented. The system comprises a modem that is configured to transfer data between an ADSL line and a USB bus and that is further configured to receive an ADSL line rate setting, submit an isochronous bandwidth request to a computer, reduce the isochronous bandwidth request in response to the availability of isochronous bandwidth, modify the ADSL line rate setting in response to the availability of isochronous bandwidth, and modify the USB bus transfer mode in response to the availability of isochronous bandwidth. The method comprises steps of receiving an ADSL line rate setting, submitting an isochronous bandwidth request to a computer, reducing the isochronous bandwidth request in response to the availability of isochronous bandwidth, modifying the ADSL line rate setting in response to the availability of isochronous bandwidth, and modifying the USB bus transfer mode of the ADSL USB modem in response to the availability of isochronous bandwidth.

Abstract: A system and method for determining fault path behavior in a computer software system. An error or event, the occurrence of which is to be tested, is assigned a probability value and an array of elements populated by pseudo-random numbers. Upon each operation of the system under test the current array value is compared against the probability value. If the current array value is greater than or equal than the probability value, the error or event is simulated within the software. Otherwise, the event is not simulated and the software is left to operate conventionally. The array is incremented upon each occurrence of the system under test.

Abstract: Methods and systems for tuning an RC continuous-time filter are disclosed. In this regard a representative system for tuning an RC continuous-time filter includes a coarse-tuned resistive element coupled to an input of the filter for varying the cut-off frequency of the filter based upon process variations. The system also includes a MOSFET transistor coupled to the resistive element. The MOSFET transistor provides a resistance dependent upon a voltage offset provided to the gate of the transistor, wherein the resistance of the transistor offsets an adjustment in the resistance of the resistive element caused by temperature variations. The system also includes a voltage offset generator configured to provide the voltage offset to the transistor.