Abstract: A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

Abstract: An improved line driver and method for increasing the available signal transmit power on a transmission line are disclosed. The improved line driver achieves an available transmit power increase by limiting the output stage signal path to NMOS and NPN bipolar semiconductor devices. The output stage of the improved line driver may comprise a first amplifier, a second amplifier, a first transformer, a second transformer, and a plurality of back-matching resistor networks. A second embodiment of an improved output stage of a line driver may comprise a first amplifier, a second amplifier, a transformer, and a plurality of back-matching resistor networks. Both preferred embodiments may be implemented with CMOS and bipolar semiconductor devices, as well as, a combination of the two semiconductor technologies.

Abstract: A method and system is disclosed for providing land-line access to customer premises equipment devices. In particular, a system and method is provided including at least one computer network service provider. A customer premises equipment device is operatively connected to the at least one service provider over a computer network, with the customer premises equipment device being configured to include a broadband modem and an analog modem. A computer is then operatively connected to the customer premises equipment device for obtaining access to the computer network through the customer premises equipment device. In accordance with the present invention, the at least one service provider may monitor and configure the customer premises equipment device by exchanging information with the analog modem, thus enabling the service providers to access and remotely monitor and configure the CPE device to meet various required protocols.

Abstract: A physical interface unit and method are disclosed which are configured to receive a data stream which may use any one of a number of data communications protocols, and to transmit the same data stream using another one of the same number of data communications protocols. The physical interface unit is advantageously designed to operate in conjunction with a processor circuit to translate a data stream from a first data protocol to a second data protocol. The physical interface unit includes a first serial interface, a first asynchronous transfer mode (ATM) interface, and a first parallel interface. The physical interface also includes a second serial interface, a second ATM interface, and a second parallel interface. The first serial, ATM, and parallel interfaces are electrically coupled to a first FIFO circuit which interfaces with the processor circuit. Likewise, the second serial, ATM, and parallel interfaces are electrically coupled to a second FIFO circuit which interfaces with the processor circuit.

Abstract: A system and method for characterizing a transmission line in a digital subscriber line (DSL) system. Broadly, the method uses DSL system components, which are configured to perform time domain reflectometry (TDR), in order to determine transmission line characteristics.

Abstract: A circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation is disclosed. The single modulo pointer of the present invention may be used to increase data throughput through a data interleaver/deinterleaver. A memory address pointer consistent with the present invention may be implemented with a multiplexer, an adder, a counter, and a modulo operator. A method for convolutional interleaving/deinterleaving is also disclosed.

Abstract: A line driver is disclosed. Generally, the structure of the line driver contains an amplifier stage that can operate at various voltage levels. The first external supply voltage is connected to a first power supply input of the amplifier stage. The line driver also includes a charge pump that generates at least a first internal supply voltage supplied to the amplifier stage. A switch control circuit is also included within the line driver to regulate the voltage output from the charge pump. Systems and methods for supplying various voltages to a load are also disclosed.

Abstract: A system and method for providing symmetrical connectivity between at least two consumer premises equipment (CPE) telecommunications devices is provided. At least two consumer premises equipment telecommunications devices are operatively connected over an asynchronous transfer mode telecommunications network. The at least two consumer premises equipment telecommunications devices are configured to perform local tone generation, local tone detection and decoding, and direct transfer and decoding of dialed digits using channel associated signaling secondary service packets and dialed digit packets to transition between various states. By providing symmetrical connectivity of CPE devices, central office involvement may be eliminated.

Abstract: The present invention is generally directed to a novel method of computing a fast Fourier transform (FFT), and an associated circuit that controls the addressing of a data memory of the FFT processing circuit. The novel method operates by computing all complex butterfly operations in a given stage of computations, before computing any of the complex butterfly operations in a subsequent stage. Further, and within any given computation stage, the method performs by computing all other complex butterfly operations in a given stage of computations having a twiddle factor equal to the first twiddle value of that stage, before computing any other complex butterfly operations in the given stage of computations. Thereafter, subsequent computations are performed in the same way.

Abstract: In general, a system and method for implementing DSL support for use by a computer having a PCI bus is disclosed. A DSL modem is allowed to simultaneously communicate data to and from the computer. In a simplified embodiment, a DSL enabling device provides both data flow control and general control functions of the DSL modem. The DSL enabling device comprises a PCI DMA arbitrator, which determines the status of a temporary memory module in response to either a transmit request from a transmit control unit or a receive request from a receive control unit, thereby arbitrating between the two control units in order to access the temporary memory module. A read/write register specifies priority between the transmit control unit and the receive control unit, as well as specifying computer memory addresses to write to and setting memory cell length.

Abstract: A resource optimized interleaving/deinterleaving system comprising a Reed-Solomon encoder, a Reed-Solomon decoder, a state machine, and a memory is disclosed. Reed-Solomon encoded fastpath data is stored in memory. A stream of interleaved data with predefined parameters S, the number of DMT symbols per each Reed-Solomon codeword, D, the interleaving depth, and N, the block length is written into system memory at an adaptable rate determined by the Reed-Solomon encoder. The previously stored Reed-Solomon encoded fastpath data is automatically reassembled and buffered with the interleaved data to form appropriate DMT transmission symbols. The DMT transmission symbols are then read out of the system memory at a rate determined by the next processing function, i.e., tone ordering. A method of using one Reed-Solomon encoder/decoder with the integrated interleaving/deinterleaving system to support dual single latency DMT systems is also disclosed.

Abstract: A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.

Abstract: A process circuit is disclosed for computing a fast Fourier transform (FFT). In one embodiment, the processing circuit includes a memory device, a multiplier, a detector, a state machine, and a circuit for performing the 2's compliment of a coefficient. The memory storage device stores data values and coefficient (or twiddle) values. The detector integrates a date pointer with the state machine. The detector is designed to identify the symmetry lines (by memory address). The state machine, when notified by the detector that a line of symmetry has been encountered, appropriately adjusts either the coefficients, the imaginary sign, or the real sign for input to a multiplier.

Abstract: In general, a system and method for providing PCI power management support without requiring a clock is disclosed. A computer is allowed to reside in a sleep mode and receive a power management event signal from an attached peripheral device in response to an external action request from an external source, thereby waking the computer and initializing device drivers to allow the peripheral device to perform predefined functions. During initiation of the power management system, the system provides a peripheral device with a PME_Status bit. In response to an external event, the peripheral device receives an external action request from the source of the external event. The peripheral device then sets the PME_Status bit and transmits a power management event (PME) signal to a computer operating system. Upon receiving the PME signal, the computer turns back on. The computer operating system then searches all peripheral devices connected to the computer for the set PME_Status bit.

Abstract: A system and method for scheduling the transmission of ATM cells is provided which includes two discrete processors. One processor examines the virtual channels and their traffic parameters, and calculates the times at which cells should be transmitted from each channel. The second processor manages multiple ATM network ports, performs low-level cell handling and the majority of cell switching, and transmits cells when instructed by the first.

Abstract: In accordance with one aspect of the invention, an apparatus is provided for facilitating combined xDSL and POTS communication across a two wire pair. The apparatus includes a first communication port for communication with a central office across a two wire pair, and a second communication port for communication with a customer premises across a two wire pair. A splitter, or tap, is disposed at the first communication port for splitting a combined xDSL and POTS signal into a first and second signal path. A low pass filter is disposed in the first signal path for filtering the xDSL signal from the combined signal in the first signal path, leaving only the low-frequency (POTS frequency) signals. A circuit is disposed in the second signal path that is configured to filter the POTS signal from the combined signal, leaving only the xDSL signal.

Abstract: The present invention is directed to an improved direct memory access (DMA) controller for executing commands having an extremely compact structure, and which may be stored in an external memory. In accordance with one aspect of the present invention, a DMA controller is provided having circuitry configured to receive a memory segment, wherein the memory segment comprises a plurality of contiguous bytes from an external memory. The DMA controller also includes circuitry configured to parse the received memory segment into a plurality of distinct segments. The controller also includes circuitry configured to store the plurality of distinct segments into a plurality of internal registers, wherein the plurality of internal registers includes a command register. Finally, the DMA controller includes circuitry configured to decide the value stored in the command register to identify an instruction for execution.

Abstract: A parallel-to-serial-to-parallel circuit are disclosed, the circuit interfacing with a data bus, preferably with a processor for byte alignment and other operations. The parallel-to-serial-to-parallel circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment.

Abstract: The present invention entails a programmable data communications protocol conversion unit (PCU) and method. The PCU is a processor circuit which includes a means for performing full parallel, partial parallel, and bit data transfers. In particular, a bit assembly register is employed to assemble partial parallel data blocks which comprise data with a number of bits that is less than the order of the data bus of the PCU. The bit assembly register further includes the capability of writing the partial parallel data block to predetermined locations using a full parallel transfer and a shadow bus with bits indicating the validity of the particular bits in the data block transferred. The particular circuits receiving partial parallel writes include a register for receiving data and a register for receiving the corresponding shadow bits. Invalid data written to these registers is ignored while valid data is shifted accordingly, for example, out to a serial interface.

Abstract: The present invention generally relates to echo cancellation over an asymmetric transmission and receiving spectra. An apparatus is provided having a transmit path and a receive path, with an adaptive echo canceler disposed therebetween, for communicating data within a first bandwidth and a second bandwidth respectively. A first decimator is disposed between the transmit path and the echo canceler circuit and filters an incoming signal having a first sampling rate and emits a signal output at a second, reduced sampling rate. A second decimator is disposed along said receive path and filters an incoming signal and emits a signal output at a reduced sampling rate. An adder is disposed to subtract the output of the adaptive echo canceler from output of the second decimator to generate a received signal that is substantially free of echo.