Abstract: A method and structure for crystallizing film is disclosed. The method includes the steps of forming a film on a substrate, forming a lens on the film to focus an electromagnetic wave on the film and directing the electromagnetic wave on the film inclusive of the lens to crystallize the film.

Abstract: A method and structure for crystallizing film is disclosed. The method includes the steps of forming a film on a substrate, forming a lens on the film to focus an electro-magnetic wave on the film and directing the electro-magnetic wave on the film inclusive of the lens to crystallize the film.

Abstract: A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.

Abstract: A MOSFET and method of manufacture thereof is disclosed in which an ion implantation layer formed in the channel region is isolated from the source and drain regions. The source and drain regions are of a lightly doped drain or "LDD" structure. According to this MOSFET and method, short channel effects are decreased by the channel implant, yet hot carrier and doping compensation effects are decreased, junction capacitance is decreased, and mobility of the carriers also may be improved.

Abstract: An improved automatic data backup apparatus for a microcomputer capable of automatically backing up a user's program at a central processing unit(CPU), which includes a central processing unit(CPU) for performing a user program and a monitor program outputted from a first emulator input/output circuit and a data/address bus; a second emulator input/output circuit for outputting a register signal applied thereto and for inputting/outputting a data between a register data bus connected to an emulator and a backup register bus; and a data backup storing circuit for automatically backing up a data stored in a register of the CPU corresponding to a user program performed in the CPU in accordance with a monitor program request signal outputted from the second emulator input/output circuit, a register signal, a register recording signal, and a register judgement signal and for applying a data stored in a register in the CPU corresponding to a user program which is changed by a backed-up monitor program.

Abstract: A semiconductor package with solder balls and a method for producing the package are disclosed. The package has no outer lead but is provided with the solder balls formed on the mold resin body, thus to allow a plurality of packages to be easily vertically layered when enlarging the memory capacity. The package producing method forms the solder balls through screen printing or dotting, or electroplating and vacuum depositing of solder paste, thus to need no typical forming step and to achieve the thinness of the package. A plurality of holes are provided in at least one of the top section and the bottom section of the mold resin body such that the holes communicate with the inner leads respectively. The solder balls are formed on the holes under the condition that a plurality of conductors are charged in the holes. The solder balls are electrically connected to the inner leads through the conductors.

Abstract: An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate and source/drain regions at the same time, the transistor particularly having a stable threshold voltage. The disclosed method provides the steps of: (A) forming an active region and an insulation region on an n-type semiconductor substrate; growing a gate insulating layer on the silicon substrate; depositing a polysilicon layer on the gate insulating layer; annealing the polysilicon layer in the presence of NH.sub.3 or other nitrogen-containing gas; (C) forming a gate line by patterning and etching the polysilicon layer; and (D) implanting BF.sub.2 ions into the semiconductor substrate.

Abstract: An improved high resolution method and apparatus are described for sensing and determining the spatial coordinates of a movable object with respect to a energized conductive surface. The coordinates of the object are precisely measured with respect to a two-dimensional coordinate system independent of the third orthogonal dimension, thereby avoiding significant measurement errors due to variations of the object position in the third orthogonal dimension. The system also ascertains the coordinate position of the object in this third dimension, which can then be utilized as an independent control variable in the system. Further, the system can accommodate a number of energized conductive surfaces over which the object may be positioned and can determine the spatial coordinates of the object with respect to any such surface.

Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

Abstract: An infrared photodetector using .delta.-doped semiconductors capable of reducing the requirement to form a quantum well structure of high quality, reducing the need of a cooling device due to the operation at the room temperature, and controlling the wavelength of infrared ray detected by controlling the .delta.-doped concentration. The infrared photodetector includes a semiconductor substrate, an active layer formed over the semiconductor substrate, .delta.-doped layers formed in the active layer, the .delta.-doped layer having a doping concentration controlled for controlling a wavelength of infrared ray detected, a current injection layer formed over the active layer, a cap layer formed over the current injection layer, and an electrode formed on the cap layer.

Abstract: A phase shift mask and method of manufacture are disclosed in which a light shielding layer is formed on a substrate and patterned to produce parallel areas of predetermined intervals and spacings of the desired shape. A phase shift film is formed on the substrate and light shielding layer. The phase shift film is patterned so that remaining portions of the phase shift film fully shield the parallel areas of the light shielding layer.

Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed in a furrow of an insulating layer, with a gate oxide and body polysilicon formed thereon, thereby allowing the source and drain level to be in a smooth plane parallel with the gate level. Steps that may be included in the disclosed method for fabricating thin film transistors having a bottom gate are: a) forming an insulating layer on a substrate, and forming a furrow by etching the insulating layer at a portion corresponding to where a gate line is to be formed; b) forming a gate line in the furrow by depositing a conductive layer, and etching back the conductive layer; c) forming a gate insulator on the gate line, forming a semiconductor layer on the gate insulator; and d) forming impurity regions at opposite sides of the gate line.

Abstract: An improved arithmetic logic operation circuit capable of advantageously reducing propagation delay due to a logic gate for obtaining a high speed arithmetic logic unit by minimizing the number of logic gates, which includes an even bit arithmetic logic unit cell for logically operating upon even bits of a first and second data and for generating a carry out signal in accordance with an inverted carry in signal, an inverted carry enable signal and an operation control signal, and an odd bit arithmetic logic unit cell for logically operating upon the odd bits of the first and second data and for generating a carry out signal in accordance with the carry in signal, a carry enable signal and the operation control signal.

Abstract: A thin film transistor and a method which forms a channel region (c), a lightly doped drain region (LDD) region and, optionally, an offset region (o), in a portion of a semiconductor layer which is adjacent a sidewall of the gate electrode without the use of photo masks, thereby increasing the permissible degree of miniaturization and improving production yield.

Abstract: A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

Abstract: A CCD for detecting images includes a substrate, a well region formed on the semiconductor substrate, a horizontal CCD (HCCD) formed in the well region, a photodiode region formed in the well region at a prescribed spacing from the HCCD, a channel stop layer, an impurity diffusion layer which serves as a potential barrier region around the side and lower portions of the photodiode region so as to completely separate the photodiode region from the well region, a gate insulating layer formed on the substrate, a polygate formed on the gate insulating layer above the HCCD, an insulating layer formed on portions of the gate insulating layer, and a metal shielding layer formed on the insulating layer, whereby a smear phenomenum is prevented.

Abstract: The invention discloses a process for formation of a capacitor for a semiconductor device. The upper node electrode is supported by side wall spacers and a central pole, so that the supporting strength may be reinforced and the surface area may be increased. During the formation of a contact hole, a first side wall spacer is formed, and, by utilizing the first side wall spacer, a contact hole is opened with a greater margin. The upper and lower node electrodes are of a tunnel structure. The central pole of the node electrodes is provided with a hole in it, so that a conductive material may be filled into the hole to form a connecting portion. This connecting portion connects the node electrodes of the capacitor to a source/drain region which is formed on a semiconductor substrate. A thin dielectric film is deposited on the surface of the node electrode, and a plate electrode is formed thereupon, thereby completing the formation of the capacitor.

Abstract: A process for the isolation of a semiconductor layer on an insulator. A process for isolating a semiconductor layer on an insulator is disclosed that includes the steps of: forming a first insulating layer on a semiconductor substrate, and opening a window by etching the first insulating layer which becomes an epitaxial growth seed; depositing a semiconductor layer and growing an epitaxial layer which has the same crystal structure as the semiconductor substrate under the window; forming an active area of the epitaxial layer by a photolithographic process; forming a second insulating layer on and at the side of the active area and on the first insulating layer; and isolating an active area from the semiconductor layer by forming a third insulator layer in the window by an oxidation process.

Abstract: A method for manufacturing a thin film transistor is disclosed.

Abstract: A method is provided for fabricating a phase shift mask of the out rigger sub-resolution type capable of accurately fabricating an ultra-fine semiconductor circuit.