Abstract: A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal volt

Abstract: An earth leakage breaker comprising a zero-phase-sequence current transformer for detecting a current difference on an AC line with respect to both positive (+) and negative (-) directions to sense an electric leakage of the AC line, a comparator for comparing an output voltage from the zero-phase-sequence current transformer with a trigger reference voltage, a delay for delaying the output voltage from the zero-phase-sequence current transformer by a desired period, a subtracter for subtracting an output voltage from the delay from the output voltage from the zero-phase-sequence current transformer, first and second level discriminators for discriminating levels of output signals from the comparator and the subtracter, respectively, first and second duration generators for generating durations in response to output signals from the first and second level discriminators, respectively, a first, pulse width generator for generating a pulse width corresponding to the duration from the first duration generator, a

Abstract: A method for forming a contact hole for a metal line in a semiconductor device, including the steps of forming a contact area on a semiconductor substrate to be connected to a metal line, forming a groove, of which side is insulated from a contact portion on a bottom and at a side of the groove, forming an insulating layer on a whole surface of the semiconductor substrate, and forming a contact hole by removing a portion of the insulating layer on the barrier metal contact portion.

Abstract: A recess is formed (dug) into the surface of a substrate to form a gate channel in the recess, so that a monocrystalline source/drain region can be formed at a level higher than that of the channel. The process includes the steps of: (a) forming an insulating layer and an oxidation preventing layer on a semiconductor substrate, and removing the oxidation preventing layer of a channel region of the transistor by an etching process; (b) forming an oxide layer on the channel region of the transistor by thermally oxidizing the semiconductor substrate, removing the oxidation preventing layer, and carrying out a first ion implantation on the whole surface; (c) removing the oxide layer, and forming the channel of the transistor in the form of a recess so as for the recess to be positioned lower than the surface of the substrate; (d) forming a gate electrode in the recess; and (e) carrying out a second ion implantation on the whole surface, and carrying out a heat treatment to form a source/drain region.

Abstract: Heartbeat collision prevention circuit and method in a network in which a plurality of stations are connected to data and heartbeat lines.

Abstract: A multi-meter comprising a switch for selecting an object and a range of a thing to be measured, a display unit for displaying a value measured according to the object and the range selected by the switch, a measurement circuit including a Z-state measurement unit to measure a Z-state of the thing to be measured, in addition to the object to be measured, the Z-state being an unknown state, and a controller for controlling the switch, the display unit and the measurement circuit. The Z-state measurement unit includes a light emitting circuit having first and second light emitting diodes. The first light emitting diode is turned on when the thing to be measured is not at the Z-state and the second light emitting diode is turned on when the thing to be measured is at the Z-state.

Abstract: A multi-chip semiconductor package and a method for manufacturing such a package. The package includes a plurality of inner leads of a lead frame, upper and lower semiconductor chips electrically connected to upper and lower surfaces of said inner leads, respectively. The upper and lower chips each has a plurality of pads each having a solder formed thereon. The solder is connected to each inner lead by a soldering, thereby causing the upper and lower chips to be electrically connected to the inner lead, respectively. The method includes the steps of forming polyimide layers on opposite sides of surfaces of the semiconductor chips, forming solders on pads of the semiconductor chips, upon locating inner leads with respect to the solders in order to be disposed at a direction, connecting the inner leads to the solders, and upon superposing an overturned chip on another chip, performing an encapsulation epoxy to the chips in order to cause the chips to be connected to each other.

Abstract: The process of the present invention is simplified by skipping the die bonding step, the wire bonding step and the trim-forming step of the conventional techniques. A semiconductor device may include: a plurality of bonding pads formed on the surface of the chip for connecting the internal circuit of the chip to an outer circuit; an insulating layer for insulating the surface of the chip, having a height higher than the height of the bonding pads, and formed on the whole surface of the chip except the portions where the bonding pads are formed; a plurality of bumps attached to the bonding pads; a plurality of pad type leads attached to the bumps; and a molding resin for covering the whole surface of the chip except the portions where the leads are disposed.

Abstract: The present invention provides a process for cleaning semiconductor devices which enables the contamination of copper to maintained under a level of about 10.sup.9 atoms/cm.sup.2 to meet the qualification of DRAMs of equal to or greater than 64M bits in capacity by means of supplying O.sub.3 to a solution, resulting in great reproducibility and reliability. According to the present invention, a mechanism for removing a copper impurity in a semiconductor device uses oxygen to form a cupric oxide, which forms a cupric fluoride, which is then removed from the solution.

Abstract: A digital/analog converter comprising a coarse bit decoder for decoding M higher-order bits of an (M+N)-bit input digital signal, a fine bit decoder for decoding N lower-order bits of the (M+N)-bit input digital signal, a current scaler for classifying currents into a plurality of steps and outputting a selected one of the classified step currents in response to an output signal from the coarse bit decoder, a current/voltage converter for converting an output current from the current scaler into a voltage, a voltage elevator for outputting an output voltage from the current/voltage converter as a reference voltage, a voltage divider for dividing the reference voltage from the voltage elevator into a plurality of steps and outputting a selected one of the divided step voltages in response to a switching control signal from the fine bit decoder, and a current compensator for compensating for an amount of current flowing through the voltage divider to make the reference voltage in the voltage divider constant in

Abstract: A method for isolating semiconductor regions so that unit elements may be electrically insulated. A disclosed method includes the steps of: forming a pad oxide layer and a nitride layer on a silicon substrate, and forming an active region pattern; exposing the pad oxide to HF to remove a portion of the pad oxide, and depositing polysilicon so that pad oxide as the path for the diffusion of oxygen during the oxidation is not exposed to the oxidizing atmosphere; forming a nitride layer side wall on the side of field region to increase the distance between field oxide region and active region; and carrying out a field channel stop ion implantation after the completion of the first field oxidation and after removing the side wall of nitride layer and before a second field oxidation process.

Abstract: A variable operation speed MOS transistor having a source, a drain and a gate with a plurality of contacts formed thereon. One end of the gate of the variable operation speed MOS transistor is connected to drains/sources of first MOS transistors, while the plurality of the contacts formed on the gate of the variable operation speed MOS transistor are connected to the drains/sources of second MOS transistors, which are of an opposite type to that of the first MOS transistors, and the source or drains of which are connected to Vcc. Input signals are supplied to the respective gates of the first and second MOS transistors in such a manner as to adjust the turn-on and turn-off speeds of the variable operation speed MOS transistor.

Abstract: A semiconductor package directly soldering the chip pad to the inner leads and a method for producing the package are disclosed. The chip pad is placed on the bottom surface of an inner lead extending from opposed sides of the chip pad. A plurality of inner lead holes are formed in the interconnection parts between the inner leads and the auxiliary leads. A solder resist film bonded to the lead frame has a plurality of solder resist holes communicating with the inner lead holes. In order to produce the package, a lead pattern is formed and the lead frame is etched using the lead pattern, so that the inner lead holes and the solder resist holes are formed and the inner leads come into direct contact with the chip pad. Thereafter, the chip pad is soldered to the inner leads.

Abstract: A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.

Abstract: A lead frame and a semiconductor package produced using the lead frame are disclosed. The lead frame has a plurality of multi-layered inner leads, each of the multi-layered inner leads having at least two different metal layers joined to each other. An outer lead is formed by an extension part of at least one of the different metal layers of each of the multi-layered inner leads. The semiconductor package includes a semiconductor chip, the lead frame and a package body hermetically packaging a predetermined volume including the semiconductor chip, the multi-layered inner leads of the lead frame and a plurality of metal wires. The lead frame is free from chip paddle, thus to improve operational reliability of the package. The semiconductor package with the lead frame is readily enlarged in its memory capacity and mounted on the surface of a PCB in various mounting types.

Abstract: 8-bit absolute value calculation method and circuit.

Abstract: A pulse generator comprises a transistor, a feed-back circuit and a second logic gate. The feed-back circuit includes a first logic gate coupled to at least one inverter, which is connected to a transmission gate. The first logic gate has a first terminal to receive a first input signal and a second terminal to receive an output of the transmission gate. The second logic gate receives an output of the feed-back circuit and a second input signal to generate an output signal. The feed-back circuit feeds back the first input signal through the first logic gate, at least one inverter and transmission gate to the second terminal of the logic gate for a prescribed period of time to change a pulse length of the first input signal.

Abstract: A test apparatus for a semi-conductor memory device comprising a memory section having a plurality of memory cell arrays, the memory cell arrays receiving input data in parallel, a latch control circuit responsive to a write enable signal and an address signal for outputting a control signal for latching the input data while the input data is written into the memory section, an expected data latch circuit responsive to the control signal from the latch control circuit and a read enable signal for latching the input data while the input data is written into the memory section and outputting the resultant expected data, a clock generator for generating a clock signal in response to a test flag signal and an internal column address select signal, an expected data transfer circuit for transferring the expected data from the expected data latch circuit in response to the test enable signal and the read enable signal, a data discrimination circuit for discriminating whether output data from the memory section are t

Abstract: An output buffer circuit for a memory device comprising a pull-up path including first and second PMOS transistors for forming two parallel charging paths, and a pull-down path including first and second NMOS transistors for forming two parallel discharging paths. The first and second PMOS transistors are selectively operated according to a level of an output voltage at an output terminal to perform a charging operation for a load capacitance connected to the output terminal. The first and second NMOS transistors are selectively operated according to the level of the output voltage at the output terminal to perform a discharging operation for the load capacitance through a lead inductance.

Abstract: A resin molded CCD package and a method for preparing the CCD package by employing a transfer molding using a low-priced plastic material having a good moldability. This package comprises a semiconductor chip as a CCD, a lead frame being integrally provided with a paddle and a plurality of leads, a film wall being attached to an upper surface of the semiconductor chip such that it surrounds a light reception region of the semiconductor chip, a glass lid for sealing the light reception region and transmitting an outside light to the region, a plurality of metal wires for electrically connecting a plurality of bond pads of the semiconductor chip to individual inner leads of the lead frame, and a mold resin package body for hermetically sealing a predetermined part including the semiconductor chip and the inner leads, both being wire-bonded to each other.