Abstract: A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the present invention includes: a buried capacitor consisting of a storage electrode, a dielectric layer and a plate electrode formed on a substrate in a planar form; and a transistor formed above the capacitor, a source/drain region of the transistor being connected to the storage electrode of the capacitor.

Abstract: A method of forming a semiconductor device by concurrently forming both single-trenched small field regions and double-trench-extension large field regions, and the device so formed.

Abstract: A static random access memory device having a power-down timer for generating a power-down signal in response to a plurality of address transition detecting signals and data input detecting signals, a chip selection detecting signal and a write mode detecting signal, is disclosed. The device includes a power-up detector for generating a power-up signal to make the power-down detecting signal be conducted, the power-up detecting signal responding to a rising of a power supply voltage.

Abstract: A mold and a method for manufacturing a semiconductor package and the semiconductor package manufactured thereby.The semiconductor package includes a chip attached to a paddle of a lead frame. And with electrically connecting the chip and inner leads of lead frame with a metal wire, a semi-finished product having electric connections is molded by using molding dies having an extrusion in a cavity for providing an opening on an upper portion of a light receiving region of the chip, and a transparent lid is provided on the upper portion of the opening of the semiconductor package.With the invention being able to provide an excellent resin semiconductor package and improved manufacturing processes, thereby reducing the manufacturing cost, enhancing a productivity and making a manufacturing process simpler.

Abstract: There is provided a method for the fabrication of multilayer electroluminescence device, comprising the steps of: forming a lower electrode with a predetermined pattern on a substrate: forming a first insulation layer on the lower electrode atop the substrate; forming a multiply luminescent layer consisting of CaS and SrS on the first insulation layer at the same temperature with that for the first insulation layer; forming a second insulation film on the luminescent layer; and forming an upper electrode with a predetermined on the second insulation layer.In the multiply luminescent layer, a plurality of CaS plies and a plurality of SrS plies are formed in such a way that the CaS plies and the SrS plies alternate with each other and the outmost upper and lower plies are formed of CaS.The constituent substances for the multiply luminescent layer, CaS and SrS, can be deposited at the same temperature and have similar lattice constants which can lead to a matched interface between the CaS and SrS plies.

Abstract: An EEPROM flash memory cell and a process for formation thereof are disclosed. The EEPROM flash memory cell includes: a source; a drain; a gate insulating layer disposed upon a channel between the source and the drain; a floating gate electrode disposed upon the gate insulating layer and facing toward the channel; and a control gate electrode disposed upon the floating gate electrode across an intermediate insulating layer; and further includes, an erasing electrode for contacting with at least one side of the floating gate electrode at least at one or more spots thereof across a tunneling insulating layer.

Abstract: An on-screen display circuit comprising a moving clock generator for generating a moving clock signal and a character moving clock signal in response to a vertical synchronous signal, the moving clock signal varying a horizontal display position value, the character moving clock signal indicating that information to be displayed on a screen has been moved by a horizontal width of one character, a horizontal position detector for generating a horizontal position signal in response to the moving clock signal and the character moving clock signal from the moving clock generator, a vertical position signal and vertical and horizontal clock signals and outputting the generated horizontal position signal to a horizontal dot clock generator, the horizontal position signal designating a horizontal position of a character to be displayed on the screen, a display off signal generator for generating a display off signal in response to the vertical and horizontal clock signals, and a RAM address generator for generating

Abstract: A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.

Abstract: The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the first storage electrode; a second contact hole on the even impurity region, the second contact hole having an insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.

Abstract: A bit line structure is disclosed.

Abstract: A video digital/analog signal converter having a structure whereby the analog elements of the video D/A converter are separated from the digital elements of the video D/A converter and of arranging current cells of each of channels to one well. The present invention includes a Red-decoder group, a Green-decoder group, and a Blue-decoder group for decoding digital data of R, G, and B color channels, respectively, which are inputted in a state synchronized to R, G, and B clocks for controlling digital data of Red, Green, and Blue color channels. A plurality of data buses transfers digital data of R, G, and B color channel decoded at the R, G, and B decoder groups. First R, G, and B current cell matrixes generate current in response to digital data of the R, G, and B color data inputted from the data buses. Second R, G, and B current cell matrixes generates current in response to digital data of the R, G, and B color channel inputted through the data buses.

Abstract: A process for packaging a solid type image pick-up device and a device produced by the packaging process. The process includes the steps of: forming a protecting layer on a light receiving region of an image pick-up chip formed on a semiconductor wafer; separating the image pick-up chip after forming the protecting layer; attaching the image pick-up chip on a lead frame and connecting leads of the lead frame to a pad of the separated image pick-up chip; sealing the chip within a chip-receiving body by molding with a resin and by using a mold having a projection, the projection extending to the protecting layer; and removing the protecting layer, and sealing a transparent plate on a cavity formed by the projection.

Abstract: A .DELTA..SIGMA. digital/analog converter comprising an interpolator for sampling an input digital signal at a desired ratio, a noise-shaping coder for quantizing an output signal from the interpolator into the coded bits and modulating a quantization error generated in the quantization, a differentiator for detecting an intersignal variation from an output signal from the noise-shaping coder, the intersignal variation indicating a difference between previous and present digital signal values, a digital logic unit for generating a desired control signal according to the intersignal variation detected by the differentiator, an internal digital/analog converter for performing charging and discharging operations in response to the desired control signal from the digital logic unit to output an analog signal corresponding to the input digital signal, and a filter for filtering an output signal from the internal digital/analog converter to remove a mixed noise therefrom.

Abstract: Recording apparatus and method for a video cassette recorder having a snow noise removing function.

Abstract: A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.

Abstract: A method for patterning a photoresist film, capable of preventing a notching phenomenon occurring upon forming a pattern of the photoresist film having a single layer structure and thereby accurately forming a pattern of a metal wiring or a gate with a desired dimension even on a layer exhibiting a severe topology by removing a portion of the photoresist film coated over the layer having a severe topology up to a depth corresponding to 30% or below of the thickness of the photoresist film to form a recess, forming an planarized inorganic material layer on the recess, and selectively removing a predetermined portion of the photoresist film under a condition that the inorganic material layer is used as a mask.

Abstract: A structure and fabrication method for a thin film transistor which is suitable for an SRAM memory cell. The thin film transistor structure includes an insulating substrate and a semiconductor layer formed as a wall on the insulation substrate. A gate insulation film is formed on the semiconductor layer and over the entire surface of the insulation substrate. A gate electrode formed on the gate insulation film at the center part of the semiconductor layer. Impurity regions are formed in the semiconductor layer on both sides of the gate electrode.

Abstract: A phase locked loop circuit comprising a reference counter, a programmable counter, a phase detector and a lock detector.

Abstract: A thin-film gas sensor and manufacturing method of the same is disclosed which includes a silicon substrate; an insulating layer formed on the surface of the silicon substrate; a heater formed in zigzag on the surface of said insulating layer; a temperature sensor formed in zigzag on the surface of the insulating layer in parallel with the heater; an interlayer insulating layer for electrically insulating the heater and temperature sensor formed on the insulating layer; a plurality of electrodes formed on the interlayer insulating layer placed between the heater and temperature sensor; a plurality of pairs of gas sensing layers disposed in an array on the electrodes and for reacting on detected gas; and a plurality of gas shielding layers formed on one gas sensing layer out of the pair of gas sensing layers and for shielding the detected gas so that the gas sensing layers do not react on the detected gas.

Abstract: A process for forming an MOS semiconductor device having an LDD structure is disclosed, which may include the steps of: forming a first insulating layer on a semiconductor substrate; forming a conductive layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a third insulating layer on the second insulating layer; forming an etch inhibiting layer pattern for forming an over-sized gate on a relevant area of the second insulating layer; removing the second and third insulating layers and the conductive layer excluding the portions protected from the etch inhibiting layer, so as to form a stacked pattern consisting of the residual second insulating layer/the third insulating layer/the conductive layer; forming a first impurity ion buried layer on a relevant portion of the semiconductor substrate utilizing the stacked pattern for formation of a source/drain region; removing the etch inhibiting layer; removing an edge portion of the remaining second insulating layer