Patents Assigned to Hitachi Device Engineering Co., Ltd.
  • Publication number: 20030214494
    Abstract: An image displaying apparatus at least including a first structure component, a second structure component, a third structure component and a displaying unit are provided, in which it is characterized that each of the first structure component, the second structure component and the third structure component has a section at which the first structure component, the second structure component and the third structure component are disposed in the order from an inside of the image displaying apparatus on a side face thereof, and each of the first structure component and the third structure component has in a part of the section a fixing portion for being fitted to the second structure component at each of positions thereon approximately equal to each other.
    Type: Application
    Filed: March 24, 2003
    Publication date: November 20, 2003
    Applicants: Hitachi Displays, Ltd, Hitachi Device Engineering Co., Ltd.
    Inventors: Shunsuke Morishita, Tomohide Oohira, Yohio Oowaki
  • Patent number: 6646371
    Abstract: A color cathode ray tube has an electron gun including a cathode structure for emitting three electron beams, a first electrode serving as a control electrode, a second electrode serving as an accelerating electrode and plural focus electrodes and an anode arranged in the order named, a phosphor screen composed of repeating patterns of three-color phosphor elements, a color selection electrode positioned the electron gun and the phosphor screen. The following inequalities are satisfied. {(L+1360×D−600)/280}2+{(P−0.16)/0.06}2≦1, L+1360×D≧600, and P≧0.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: November 11, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Kenichi Watanabe, Shinichi Kato, Hirotsugu Sakamoto
  • Publication number: 20030202142
    Abstract: In a liquid crystal display device comprising a substrate which has an organic material film (e.g. a leveling layer, or an alignment film) and a conductive oxide film (e.g. an electrode) covering at least a part of the organic material film both formed on an inner surface thereof facing a liquid crystal layer, the present invention provides the conductive oxide film formed at a temperature being neither higher than a thermal decomposition temperature of the organic material film nor lower than a heat deflection temperature of the organic material film, so as to prevent blebs from foaming from the organic material film and appearing in the liquid crystal layer even after a long term storage of the liquid crystal display device or even external force applied to the liquid crystal display device.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Applicants: Hitachi Displays, Ltd., Hitachi Device Engineering Co, Ltd.
    Inventors: Akira Ishii, Miyo Shimizu, Shigeru Matsuyama
  • Publication number: 20030201991
    Abstract: The present invention provides a liquid crystal display device which can be used in a miniaturized portable equipment, wherein the liquid crystal display device integrally incorporates a drive circuit therein so that a circuit scale can be miniaturized. A liquid crystal drive circuit includes a first drive circuit and a second drive circuit which is mounted on one side of the liquid crystal display panel. One output of the first drive circuit is connected to a plurality of signal lines and the second drive circuit supplies signals to the first drive circuit. The liquid crystal display panel includes holding capacitive elements and signals are supplied to the holding capacitive elements from the second drive circuit. The second drive circuit includes a booster circuit for supplying signals to the first drive circuit and the holding capacitive elements.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 30, 2003
    Applicants: Hitachi Displays, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Mitsuru Goto, Yuichi Numata, Masato Sawahata, Akira Ogura
  • Patent number: 6639348
    Abstract: A color cathode ray tube includes an evacuated envelope having a generally rectangular panel portion, a narrow neck portion having a circular cross-section and a funnel portion tapering down from a panel-portion side thereof toward a neck-portion side thereof for connecting the panel portion and the neck portion, a three-color phosphor screen formed on an inner surface of the panel portion, an electron gun housed in the neck portion, and an internal conductive film extending from an inner wall of the neck portion to an inner wall of the funnel portion. The funnel portion is provided with a yoke-mounting portion of generally truncated quadrilateral-pyramidal shape for mounting a beam deflection yoke therearound on the neck-portion side of the funnel portion. The internal conductive film is formed of a first part and a second part, the first part is formed of graphite, metallic oxide and potassium silicate, and the second part is formed of graphite and potassium silicate.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: October 28, 2003
    Assignees: Hitachi, Ltd, Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Ito, Shunichi Matsumoto, Kiyoshi Sento, Kazuyuki Nishimura, Nobuhiko Hosotani, Masatoshi Akiyama
  • Patent number: 6636437
    Abstract: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: October 21, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Naoki Kobayashi, Hideaki Kurata, Katsutaka Kimura, Takashi Kobayashi, Shunichi Saeki
  • Patent number: 6636190
    Abstract: A liquid crystal display device includes a liquid crystal display panel and a lighting device. The lighting device is supplied with alternately a first current during a period t1 and a second current during a second period t2 such that electric power E1 is lower than electric power E2. E1 is defined as (t1×ip-p(1)×Vp-p(1))/2+(t2×ip-p(2)×Vp-p(2))/2, where ip-p(1)=a peak-to-peak value of the first current, Vp-p(1)=a peak-to-peak value of a voltage across the light source during the period t1, ip-p(2)=a peak-to-peak value of the second current, and Vp-p(2)=a peak-to-peak value of a voltage across the light source during the period t2. E2 is defined as (t1+t2)×Ieff×Veff, where Ieff and Veff are effective values of the current and voltage of the light source, respectively.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: October 21, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Junichi Hirakata, Kikuo Ono, Akira Shingai
  • Patent number: 6633274
    Abstract: In conventional liquid crystal display controllers such as for portable telephone sets, the display is reduced in the stand-by state but the liquid crystal display duty is not changed, i.e., even the common electrodes of the rows that are not producing display are scanned, and the consumption of electric power is not decreased to a sufficient degree in the stand-by state. A liquid crystal display controller (2) includes a drive duty selection register (34) capable of being rewritten by a microprocessor (1), and a drive bias selection register (32). When the display is changed from the whole display on a liquid crystal display panel (3) to a partial display on part of the rows only, the preset values of the drive duty selection register and of the drive bias selection register are changed, so that the display is selectively produced on a portion of the liquid crystal display panel at a low voltage with a low-duty drive.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: October 14, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Yoshikazu Yokota, Kunihiko Tani, Gorou Sakamaki, Katsuhiko Yamamoto, Takashi Yoneoka, Kazuhisa Higuchi, Kimihiko Sugiyama
  • Patent number: 6633279
    Abstract: A touch panel including an upper substrate (4A) consisting of a soft film having an upper resistor film (51) and a lower substrate of a hard plate having a lower resistor film, which are bonded together to face each other. The touch panel provides a detection output representing the position of contact between the upper resistor film (51) and the lower resistor film as two-dimensional coordinate values. Either the upper resistor film (51) or the lower resistor film or both are of a comb shape having a plurality of resistive lines with a common connector (41) at one end.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: October 14, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Masao Kono, Shinsaku Chiba
  • Patent number: 6628261
    Abstract: A drive circuit for a liquid crystal display apparatus and a large-sized liquid crystal display apparatus integrated with the drive circuit and having a reduced area occupied by the circuits. The drive circuit includes sample/hold circuits for sampling the input voltage at a predetermined timing, comparator circuits for comparing the output of the sample/hold circuits with the voltage of the signal line VD(i), switches for controlling the output voltage of the signal line, a voltage supply circuit constituted as an image signal control circuit for supplying a voltage to the switches, and control circuits for controlling the switches in accordance with the output of the comparator circuits. For the liquid crystal display panel drive circuit configured as described above, the signal line is controlled by the switches, and therefore the area occupied by the drive circuits can be reduced.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: September 30, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hideo Sato, Yoshiro Mikami, Makoto Tsumura, Genshiro Kawachi, Tatsuya Ohkubo, Shigeo Shimomura, Kenkichi Suzuki, Masanao Yamamoto
  • Patent number: 6625079
    Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the column address signal transition detector.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hideharu Yahata, Masashi Horiguchi, Yoshikazu Saitoh, Yasushi Kawase
  • Patent number: 6617610
    Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: September 9, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
  • Patent number: 6611312
    Abstract: The present invention provides a display device which can maintain a gap between a front surface panel 1 and a back surface panel 2 at a given value and maintain the air-tightness of a sealed space defined between the front surface panel 1 and the back surface panel 2 even when the gap is relatively large. To achieve such an object, the display device includes the back surface panel 1, the front surface panel 2 and the outer frame 3, the outer frame 3 is constituted of a plurality of divided wall members 3X1, 3X2, 3Y1, 3Y2 and 3C1 to 3C4. Further, at least at some portions where neighboring wall members are engaged with each other, oblique surfaces 3P are formed and a crossing angle which is made by a normal line of the oblique surfaces 3P and a normal line of the back surface panel 1 or the front surface panel 2 is set to an acute angle.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: August 26, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Yuuichi Kijima, Shigemi Hirasawa, Hiroshi Kawasaki
  • Patent number: 6610569
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: August 26, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6603527
    Abstract: A liquid crystal display device is provided with a driver circuit which can cope with an increase in the number of pixels per device. The liquid crystal display device has signal lines for driving individual pixels and a driver circuit connected to the signal lines, on a liquid-crystal-side surface of either one of substrates disposed to oppose each other with a liquid crystal interposed therebetween. The driver circuit includes a film substrate, interconnection layers formed on a surface of the film substrate, and a semiconductor chip mounted on the film substrate, and bumps are formed on the semiconductor chip inwardly of the periphery thereof. Some of the interconnection layers are connected to the bumps of the semiconductor chip, and then run under the semiconductor chip and extend to the periphery of the film substrate.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: August 5, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroko Hayata, Mitsuru Goto, Hideaki Abe, Satoshi Namiki
  • Patent number: 6597092
    Abstract: In a shadow mask color cathode ray tube, its shadow mask is not easily deformed into a concave shape when an impact or a vibration is applied to the shadow mask, so that a good image can be displayed. The electron beam passing holes of the shadow mask are each formed of an upper hole etched from the panel side of the shadow mask and a lower hole etched from the electron-gun side of the shadow mask. In each electron beam passing hole located in the peripheral portion of the shadow mask, the ratio of an upper-side etching quantity to a lower-side etching quantity is controlled to be 1.8 or less. By adjusting the balance in strength relative to compressive stresses between the panel side and the electron-gun side of the shadow mask, it is possible to prevent the shadow mask from being deformed into a concave shape.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: July 22, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takeharu Furusawa, Nobuhiko Hosotani, Yoshiki Nakano, Hideyuki Ohsaka
  • Patent number: 6593920
    Abstract: A level converter circuit includes an input terminal adapted to be supplied with a signal swinging from a first voltage to a second voltage lower than the first voltage; a first transistor having a gate electrode connected to the input terminal, and a source electrode connected to ground potential; a second transistor having a gate electrode connected to a drain electrode of the first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal; a load circuit connected between the gate electrode of the second transistor and the supply voltage; a third transistor having a source electrode connected to the input terminal, a drain electrode connected to the output terminal, and a gate electrode supplied with a DC voltage higher than the second voltage and lower than the first voltage.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: July 15, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Haruhisa Okumura, Yukihide Ode
  • Patent number: 6587602
    Abstract: There is disclosed a resolution conversion apparatus for converting an original digital image into a digital image having a different number of pixels in accordance with an instructed conversion magnification factor. In the apparatus, a determination circuit determines the number of pixels to be interpolated in each block of the original image and positions where they are interpolated in accordance with the conversion magnification factor. The block includes a predetermined number of pixels of the original image. A converted image generation circuit generates pixel data for the interpolation pixels at the positions where they are interpolated in accordance with a predetermined interpolation equation whose coefficients are determined with the positions and data values of the pixels in the block, and combines the pixel data for the digital original image and the generated pixel data to output a converted digital image. The interpolation equation includes spline functions and Bezier functions.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: July 1, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Shinji Wakisawa, Naruhiko Kasai, Hiroko Sato, Youichi Watanabe, Hiroyuki Koizumi
  • Patent number: 6584031
    Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: June 24, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
  • Publication number: 20030098648
    Abstract: Electroluminescence elements mounted on a substrate of an OLED display device are sealed by a protective film made of synthetic resin with chemical reaction curing in place of a sealing can. The protective film is formed such that a thickness thereof is equal to or larger than a thickness of the substrate. Alternatively, the protective film is formed by laminating a plurality of resin films which differ in one of the water absorption ratio, the elastic modulus and the hardness. With respect to the protective film which is formed of a plurality of laminated films, compared to the protective film at the electroluminescence element side, the protective film which covers the former protective film has the water absorption ratio, the elastic modulus or the hardness larger than the water absorption ratio, the elastic modulus or the hardness of the former protective film.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 29, 2003
    Applicant: Hitachi, Ltd. and Hitachi Device Engineering Co. Ltd.
    Inventors: Hiroaki Miwa, Katsuhiko Ishii, Setsuo Kobayashi, Yuji Mori