Patents Assigned to Hitachi Device Engineering Co., Ltd.
  • Publication number: 20040150603
    Abstract: In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the plural
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicants: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Yoshihiro Imajo, Tetsuro Izawa, Kimitoshi Ohgiichi, Hiroshi Okawara, Shiro Ueda, Nobuyuki Ishige, Tetsuya Kawamura, Hisashi Ishino, Fumiaki Komori
  • Publication number: 20040150780
    Abstract: In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the plural
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicant: Hitachi, Ltd. and Hitachi Device Engineering Co., Ltd.
    Inventors: Yoshihiro Imajo, Tetsuro Izawa, Kimitoshi Ohgiichi, Hiroshi Okawara, Shiro Ueda, Nobuyuki Ishige, Tetsuya Kawamura, Hisashi Ishino, Fumiaki Komori
  • Patent number: 6771332
    Abstract: A flexible substrate mounting the light sources thereon realizes a shape which can eliminate a largely projecting portion and a liquid crystal display device which uses such a flexible substrate is obtained. A strip-like portion is formed by providing an elongated cut in a flexible substrate and light sources are mounted on the strip-like portion. Due to such a constitution, the strip-like portion mounting the light sources 5 thereon has a shape which is substantially arranged parallel to the shape of the main portion 8 which occupies a most portion of the flexible substrate land hence, it is possible to eliminate a largely projecting portion. Then, the light sources 5 are arranged such that the strip-like portion is folded back at least once such that light from the light sources is incident on a light guide body 4.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: August 3, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventor: Takahiro Yamada
  • Patent number: 6765840
    Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: July 20, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroshi Sato, Shoji Kubono, Toshinori Harada, Takayuki Kawahara, Naoki Miyamoto
  • Patent number: 6753099
    Abstract: The present invention provides a green emitting phosphor which includes an excess of the ordinary SiO2 component included in parent material Y2−2xSiO5 activated by Tb in terms of stoichiometric ratio. The composition of the above phosphor is represented by chemical formula: {(Y1−y−zMyGdz)1−xTbx}2(Si1−bGebO2)1+aO3 where values of x, y, z, a, and b are assigned, subject to 0<x≦1, 0≦y≦1, 0≦z≦1, 0<a≦1, and 0≦b≦1, and M is at least one element selected from a group comprising Sc, In, La, Lu, Yb, Ce, Eu, Sm, Tm, Ho, Er, and Nd. By using this phosphor, phosphors that emit light of higher luminance with less luminance degradation and are suitable for high-quality image display and imaging devices producing high-quality images are obtained.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 22, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Kasei Optonix, Ltd.
    Inventors: Shin Imamura, Masatoshi Shiiki, Masaaki Komatsu, Hidetsugu Matsukiyo, Yoshihiro Koseki, Takashi Hase, Tsutomu Yamada
  • Patent number: 6750926
    Abstract: Drain driver output terminals (lead lines) are divided into six groups (R1, R2, G1, G2, B1, B2) of positive polarity and negative polarity for three primary colors: respective ones are bundled together for connection to drain line common lines; and then, these drain line common lines are drawn out of a drain driver mount region. Gate driver output terminals (lead lines) are divided into three groups (GA, GB, GC) including a front stage and a next stage plus a rear stage; and respective ones are bundled together for connection to gate line common lines. These gate line common lines are drawn out of a gate driver mount region; and then, tests are preformed with probes attached to test terminals provided at such drain line common lines and gate line common lines.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: June 15, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Kimitoshi Ohgiichi, Ryouichi Ootsu, Kazushi Miyata, Shinichi Tsuruoka, Susumu Niwa
  • Patent number: 6747509
    Abstract: It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: June 8, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Masashi Horiguchi, Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, Kazuhiko Kajigaya
  • Patent number: 6747628
    Abstract: In conventional liquid crystal display controllers such as for portable telephone sets, the display is reduced in the stand-by state but the liquid crystal display duty is not changed, i.e., even the common electrodes of the rows that are not producing display are scanned, and the consumption of electric power is not decreased to a sufficient degree in the stand-by state. A liquid crystal display controller (2) includes a drive duty selection register (34) capable of being rewritten by a microprocessor (1), and a drive bias selection register (32). When the display is changed from the whole display on a liquid crystal display panel (3) to a partial display on part of the rows only, the preset values of the drive duty selection register and of the drive bias selection register are changed, so that the display is selectively produced on a portion of the liquid crystal display panel at a low voltage with a low-duty drive.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: June 8, 2004
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Yoshikazu Yokota, Kunihiko Tani, Gorou Sakamaki, Katsuhiko Yamamoto, Takashi Yoneoka, Kazuhisa Higuchi, Kimihiko Sugiyama
  • Publication number: 20040103328
    Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.
    Type: Application
    Filed: November 7, 2003
    Publication date: May 27, 2004
    Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Toru Ichien, Wataru Yamaguchi, Masae Sasakawa, Mamoru Wakabayashi
  • Patent number: 6741299
    Abstract: In order to install a liquid crystal display device comprising a liquid crystal display element, a frame being arranged at a displaying surface side thereof, a light source being arranged at an opposite side to the displaying surface side, and a housing member for housing the light source to an exterior case easily and surely, the present invention provides a screw member to which a fitting screw for fixing the liquid crystal display device to the exterior case is screwed at a side wall of the housing member, a protruded portion being protruded in a thickness direction of the liquid crystal display device at the side wall having the screw member, and an opening which the protruded portion is inserted into in the frame, respectively.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: May 25, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Norihisa Fukayama, Naoto Kobayashi, Fumitoshi Matsuda, Yoshihiro Imajo, Yoko Ota
  • Patent number: 6734941
    Abstract: In a liquid crystal display device having a flexible printed circuit board which includes a laminated structure of a pair of flexible films, a plurality of first conductive layers interposed between inner surfaces of the flexible films to be spaced from each other, and a plurality of groups of terminals formed on an outer surface of one of flexible films opposite to the respective first conductive layers, and a liquid crystal display panel which includes a plurality of groups of wirings formed on one of a pair of substrates thereof and connected to the plurality of groups of terminals respectively, the present invention interposes second conductive layers at respective portions spacing the plurality of first conductive layers between the inner surfaces of the flexible films and prevents the one of the pair of substrates from being cracked when the plurality of terminals of the flexible printed circuit board are connected to the groups of wiring of the one of the substrates by compression bonding thereby.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: May 11, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiroyuki Yamazaki, Tomio Oosone, Tetsuya Kawamura
  • Publication number: 20040085690
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Applicants: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 6731056
    Abstract: A color cathode ray tube having at least an electron gun, constituted by a cathode for forming a plurality of electron beams arranged in-line, and a focusing electrode and an anode constituting a main lens for focusing and accelerating the electron beams and a fluorescent screen. The focusing electrode includes at least a first division electrode and a second division electrode arranged with a gap for controlling a scanning speed of the electron beams in common. The second division electrode is opposed to the anode and has, in an opposed surface thereof, a single opening for passing the plurality of electron beams in common. A length of the first division electrode in the axial direction of the tube is longer than a length of the second division electrode in the axial direction of the tube.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 4, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Tsutomu Tojo, Hiroyuki Tamura, Masayoshi Misono
  • Patent number: 6731263
    Abstract: Each video signal driver circuit in a liquid crystal display device includes a first amplifier circuit with a first output terminal and first and second input terminals; a second amplifier circuit with a second output terminal and third and fourth input terminals; a first connecting circuit switchable between a first connection wherein an output voltage from the first output terminal is input to the first input terminal as a reference voltage, and a second connection wherein the output voltage from the first output terminal is input to the second input terminal as a reference voltage; and a second connecting circuit switchable between a third connection wherein an output voltage from the second output terminal is input to the third input terminal as a reference voltage, and a fourth connection wherein the output voltage from the second output terminal is input to the fourth input terminal as a reference voltage.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: May 4, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Mitsuru Goto, Hiroshi Katayanagi, Yukihide Ode, Yoshiyuki Saitou, Koichi Kotera
  • Patent number: 6724659
    Abstract: In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: April 20, 2004
    Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Shunichi Saeki, Hideakii Kurata, Naoki Kobayashi
  • Patent number: 6721019
    Abstract: There is provided a highly reliable screen input type display device using a touch panel which can facilitate the control of a gap formed between upper and lower substrates and can stabilize the linearity of the resistance value detection of a resistance film, whereby an erroneous detection of coordinated can be eliminated. For this purpose, a tape-like conductive pressure sensitive adhesive member, which is formed by sandwiching a metal foil with conductive pressure sensitive adhesive material, is used at a connection portion between an upper wiring electrode mounted on an upper resistance film formed on an upper substrate and an inter-substrate connection wiring electrode formed on a lower substrate.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: April 13, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd., Hitachi Chiba Electronics, Ltd.
    Inventors: Masao Kono, Akira Kakinuma, Koji Ishii, Haruhisa Otsuka, Kazuo Ishii
  • Publication number: 20040068590
    Abstract: In this data processor, the semiconductor chip comprises a central processing unit, an interface controller, and a bus controller. The interface controller further includes an interface control unit, a FIFO unit, and a transfer control unit. The interface control unit outputs the data of the FIFO unit to the external side of the semiconductor chip and inputs the data inputted from the external side of the semiconductor chip to the FIFO unit. The transfer control unit performs the control to transfer the data stored in the FIFO unit by designating the transfer destination address and the control to input the data to the FIFO unit by designating the transfer source address. The control by the data transfer control device is not included in the transfer control by the transfer control device. Accordingly, the time required for the data transfer between the on-chip interface controller and the external side can be curtailed.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 8, 2004
    Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Tatsuo Nishino, Mamoru Wakabayashi, Toru Ichien
  • Patent number: 6717352
    Abstract: A gap defined between cathode wires 2 having electron emitting sources 2a and control electrodes 4 is made uniform and a thickness of an insulation layer 3 interposed between both of them is made thin or the insulation layer 3 is eliminated whereby the electron emission characteristics and the high-frequency driving of high performance can be realized. The control electrodes 4 which have recessed portions 4c in plate-like members and have holes 4a for allowing electrons to pass therethrough in bottom portions thereof restrict the gap defined between the cathode wires 2 and the control electrodes 4 by adjusting a plate-thickness direction size of the holes 4a formed in the control electrodes 4.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: April 6, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Shigemi Hirasawa, Kenji Miyata, Tomio Yaguchi, Yuuichi Kijima, Hiroshi Kawasaki
  • Patent number: 6717877
    Abstract: A semiconductor integrated circuit device includes a first variable delay circuit which delays a timing signal for activating a sense amplifier which is supplied with a signal read out from a memory array and amplifies the signal so that a timing difference between a dummy signal read out from a dummy memory cell and the timing signal of the sense amplifier is detected by a detection circuit to be made small in accordance with an output of the detection circuit, and a second variable delay circuit which adjusts a relative timing difference between the dummy signal and the timing signal of the sense amplifier.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: April 6, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takeshi Suzuki, Shigeru Nakahara, Keiichi Higeta, Takeshi Kusunoki
  • Patent number: RE38516
    Abstract: Herein disclosed are a liquid crystal display device and a data processing device, which can have their frame portions reduced in area to reduce the size and weight by extracting the terminals of video signals to only one side of a liquid crystal display panel and by arranging a video signal line driving circuit substrate to be connected with the terminals, only at one side of the display panel. A liquid crystal display includes upper and lower casings for holding a liquid crystal display panel and substrates. The casings are provided with at least one of fixing pawls and recesses for receiving the fixing pawls so as to enable the connection of the casings.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: May 18, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Kaoru Hasegawa, Yoshio Toriyama, Naoto Kobayashi, Katsuhiko Yarita, Hironori Kondo, Masahiko Suzuki, Yoshihiro Imajo