Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.

Abstract: A display device can realize the highly efficient electron emission characteristics by ensuring the exposure of carbon nanotubes 13 in the inside of a vacuum by fixing the carbon nanotubes 13 to cathode wires 12 such that the carbon nanotubes 13 are not easily removed from the cathode wires 12 with the small resistance which enables the carbon nanotubes 13 to have the enough electron emission ability. Some end portions or some intermediate portions of the carbon nanotubes 13 are embedded into the cathode wires 12 formed on a rear substrate 11 and, at the same time, contact points where the carbon nanotubes 13 cross each other or portions in the vicinity of the crossing portions are bonded to each other by bonding films 14.

Abstract: A liquid crystal display device includes a liquid crystal display panel and a lighting device. The lighting device is supplied with alternately a first current during a period t1, and a second current during a second period t2 such that electric power E1 is lower than electric power E2. E1 is defined as (t1×ip−p(1)×Vp−p(1))/2+(t2×ip−p(2)×Vp−p(2))/2, where ip−p(1)=a peak-to-peak value of the first current, Vp−p(1)=a peak-to-peak value of a voltage across the light source during the period t1, ip−p(2)=a peak-to-peak value of the second current, and Vp−p(2)=a peak-to-peak value of a voltage across the light source during the period t2. E2 is defined as (t1+t2)×Ioff×Voff, where Ioff and Voff are effective values of the current and voltage of the light source, respectively.

Abstract: A liquid crystal display device capable of improving display quality by enabling proper execution of receipt and acceptance of image signals through compensation for variation in duty ratios of clock signals as input to liquid crystal driver circuitry, is provided.

Abstract: The present invention provides a liquid crystal display device which can obviate cutting off of a peripheral region of the liquid crystal display device which is provided with an inspection circuit and can surely perform the inspection of an image display even when the peripheral region is narrowed on a substrate of the liquid crystal display device, a pixel region which is comprised of a plurality of gate lines and a plurality of drain lines and a peripheral region which surrounds the pixel region are formed. A turn-on inspection terminal of the liquid crystal display device are formed on the peripheral region and a semiconductor chip for driving liquid crystal is formed on the inspection terminal. The semiconductor chip is electrically insulated from the inspection terminal.

Abstract: A clock generation circuit including a clock duty adjusting circuit in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of an external clock. When the phase of the rising edge is matched with the reference clock, the duty of an output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.

Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.

Abstract: A liquid crystal is interposed between a first transparent substrate having first electrodes and a second transparent substrate having other electrodes. Pixel regions are formed at portions where the first electrodes and the other electrodes are opposed to each other. A semitransparent reflecting film is formed between the first transparent substrate and the first electrodes. The semitransparent reflecting film is formed with light transmission apertures in each pixel region. The semitransparent reflecting film also occupies portions corresponding to the gaps between the adjacent pixel regions. Alternatively, in addition to the light transmission apertures, the semitransparent reflecting film is formed with slits at positions corresponding to the gaps between the adjacent pixel regions. A light absorption film is formed between the first transparent substrate and the semitransparent reflecting film at positions corresponding to the slits, or the slits are charged with a light absorption film.

Abstract: In a liquid crystal display comprising a plurality of pixels each of which has an switching element, a plurality of drain drivers and gate drivers for operating the switching elements and the pixels, and a plurality of drain lines and gate lines supplying signals from the drain drivers and the gate drivers to the switching elements being formed on one of a pair of substrates sandwiching a liquid crystal layer, the present invention provides wiring lines formed on the one of a pair of substrates for transferring display data signals and a clock signal between each pair of the plurality of drain drivers adjacent to one another, and provides at least one gate circuit for at least one of the plurality of drain drivers which is controlled by the clock signal and switches the display data signals and the clock signal either (1) to be acquired by the at least one of the plurality of drain drivers or (2) to be transferred to another of the plurality of drain drivers arranged adjacent to the at least one of the plural

Abstract: In a semiconductor integrated circuit device including a third gate, the present invention improves miniaturization and operation speed and reduces a defect density of an insulator film. In a semiconductor integrated circuit device including a well of a first conductivity type formed in a semiconductor substrate, a source/drain diffusion layer of a second conductivity type inside the well, a floating gate formed over the semiconductor substrate through an insulator film, a control gate formed and isolated from the floating gate through an insulator film, word lines formed by connecting the control gates and a third gate formed and isolated from the semiconductor substrate, the floating gate and the control gate through an insulator film and different from the floating gate and the control gate, the third gate is buried into a space of the floating gates existing in a direction vertical to the word line and a channel.

Abstract: A display device has a driver including a level converter formed of polysilicon MISTFTs. The level converter includes first, second and third N-channel MISTFTs (NMISTFTs) and first, second and third P-channel MISTFTs (PMISTFTs). Gate and first terminals of the first NMISTFT and PMISTFT, and a gate terminal of the third PMISTFT are coupled to an input terminal via a capacitance. Second terminals of the second NMISTFT and PMISTFT, and a gate terminal of third NMISTFT are coupled to the input terminal via a capacitance. A first terminal of the third PMISTFT, and second terminals of the first NMISTFT and PMISTFT are coupled to a high voltage. A second terminal of the third NMISTFT, gate and first terminals of the second NMISTFT and PMISTFT are coupled to a low voltage. A second terminal of the third PMISTFT and a first terminal of the third NMISTFT are connected to an output terminal.

Abstract: In a display device including a display panel and a multi-layered printed circuit board which is arranged along one side of the display panel and is electrically connected to a plurality of leads of the display panel through a plurality of tape carrier packages, according to the present invention, a plurality of slits or notches are formed in a sheet fiber member which is impregnated with resin and constitutes a base sheet of the multi-layered printed circuit board along one side of the display panel. The discontinuity of the sheet fiber member formed by the slits or the notches absorbs the difference in thermal expansion of the multi-layered printed circuit board and the display panel due to the change of an ambient temperature of the display device and hence, it is possible to prevent peeling of the tape carrier package from the display panel or breaking of the tape carrier package per se.

Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.

Abstract: The present invention concerns an information access device for utilizing a supposed information service, which possesses an information-inputting device. The information access device according to one embodiment of the present invention comprises a usage discrimination part which judges whether the information-inputting device is utilized for said intended information service or unintended usage, based on prescribed information from said information inputting device.

Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.

Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

Abstract: A liquid crystal display is provided with respective signal lines and a semiconductor chip. Respective output bumps of the semiconductor chip are connected to corresponding respective signal lines through ax anisotropic conductive layer. The respective output bumps include a first group of output bumps which are arranged at a side close to the signal lines and a second group of output bumps which are arranged at a side remote from the signal lines. The area of respective bumps of the second group of output bumps which face the signal lines in an opposed manner is set larger than the area of respective bumps of the first group of output bumps which face the signal lines in an opposed manner. Due to such a constitution, a reliable connection between the mounted semiconductor integrated circuit and the signal lines is ensured.

Abstract: A level converter circuit includes an input terminal adapted to be supplied with a signal swinging from a first voltage to a second voltage lower than the first voltage; a first transistor having a gate electrode connected to the input terminal, and a source electrode connected to ground potential; a second transistor having a gate electrode connected to a drain electrode of the first transistor, a source electrode connected to a supply voltage, and a drain electrode connected to an output terminal; a load circuit connected between the gate electrode of the second transistor and the supply voltage; a third transistor having a source electrode connected to the input terminal, a drain electrode connected to the output terminal, and a gate electrode supplied with a DC voltage higher than the second voltage and lower than the first voltage.

Abstract: A color cathode ray tube has an electron gun including three in-line cathodes, first and second grid electrodes arranged in the order named, and plural electrodes for focusing three electron beams from the cathodes onto the phosphor screen. The following inequalities are satisfied: E≦1.4A−0.2B−2.7C−2D, and A≦0.35 mm, where A (mm) is a diameter of an electron-beam transmissive aperture in the first grid electrode, B (mm) is a diameter of an electron-beam transmissive aperture in the second grid electrode, C (mm) is a thickness of a portion of the first grid electrode immediately surrounding the electron-beam transmissive aperture in the first grid electrode, D (mm) is a spacing between the cathodes and the electron-beam transmissive aperture in the first grid electrode, and E (mm) is a spacing between the first grid electrode and the second grid electrode.

Abstract: An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing.