Patents Assigned to Hitachi Kokusai Electric Inc.
  • Patent number: 10128128
    Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 13, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi Takeda, Hiroshi Ashihara, Naofumi Ohashi, Toshiyuki Kikuchi
  • Patent number: 10128104
    Abstract: A method of manufacturing a semiconductor device includes forming a film on a substrate by overlapping the following during at least a certain period: (a) supplying a first source to the substrate, the first source including at least one of an inorganic source containing a specific element and a halogen element and an organic source containing the specific element and the halogen element; (b) supplying a second source to the substrate, the second source including at least one of amine, organic hydrazine, and hydrogen nitride; and (c) supplying a third source to the substrate, the third source including at least one of amine, organic hydrazine, hydrogen nitride, and organic borane.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 13, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Publication number: 20180321464
    Abstract: An imaging apparatus includes an AF evaluation value calculation unit for calculating an AF evaluation value by integrating a focus differential signal value. The AF evaluation value calculation unit includes a high luminance region determination unit for extracting a feature of each pixel value and determining whether or not the feature is a backlight scene in a dark place, and a band determination unit for determining a band of a contour component of a subject. A focus differential signal value on a low luminance region side in a contour component formed by a boundary between a high luminance region and a low luminance region due to backlighting is excluded from the integration, and the AF evaluation value is calculated using only a focus differential signal value on the high luminance region side in the contour component of the subject to be focused as an object for the integration.
    Type: Application
    Filed: October 18, 2016
    Publication date: November 8, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: KIYOTAKA KOGO
  • Patent number: 10121650
    Abstract: A technique capable of forming a film at the bottom of a deep hole having a high aspect ratio. A method of manufacturing a semiconductor device, including: (a) loading a substrate having a hole into a transfer space via a substrate loading/unloading port; (b) moving the substrate to a processing space; (c) forming a precursor in the hole by simultaneously supplying a first process gas to the substrate in the processing space and an inert gas into the transfer space with the processing space spatially connected to the transfer space and maintaining a difference between a first inner pressure of the processing space and a first inner pressure of the transfer space within a predetermined range; and (d) forming a thin film in the hole after performing (b).
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 6, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventor: Tsukasa Kamakura
  • Patent number: 10121654
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: November 6, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshinobu Nakamura, Kiyohiko Maeda, Yoshiro Hirose, Ryota Horiike, Yoshitomo Hashimoto
  • Patent number: 10121651
    Abstract: A technique capable of forming a side wall of a gate electrode having high resistance-to-etching and low leakage current is provided. A method of manufacturing a semiconductor device according to the technique includes: (a) loading a substrate into a processing space in a process vessel, the substrate having thereon a gate electrode and an insulating film formed on a side surface of the gate electrode as a side wall; and (b) forming an etching-resistant film containing carbon and nitrogen on a surface of the insulating film by supplying a carbon-containing gas into the processing space.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Arito Ogawa, Shin Hiyama
  • Publication number: 20180315651
    Abstract: Described herein is a technique capable of providing a semiconductor device having good characteristics. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate into a process chamber; and (b) forming a stacked etch stopper film by performing: (b-1) forming a first etch stopper film containing a first element and a second element by supplying a first element-containing gas and a second element-containing gas onto the substrate; and (b-2) forming a second etch stopper film containing the first element, the second element and a third element by supplying the first element-containing gas, the second element-containing gas and a third element-containing gas onto the first etch stopper film.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 1, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi TAKEDA, Naofumi OHASHI, Toshiyuki KIKUCHI
  • Patent number: 10115583
    Abstract: There is provided a method of manufacturing a semiconductor device which includes: supplying a process gas to a process chamber in a state in which a substrate with an insulating film formed thereon is mounted on a substrate support part inside the process chamber; supplying a first power from a plasma generation part to the process chamber to generate plasma and forming a first silicon nitride layer on the insulating film; and supplying a second power from an ion control part to the process chamber in parallel with the generation of plasma, to form a second silicon nitride layer having lower stress than that of the first silicon nitride layer on the first silicon nitride layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 30, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Hiroshi Ashihara, Kazuyuki Toyoda, Naofumi Ohashi
  • Publication number: 20180308681
    Abstract: There is provided a technique that includes forming a nitride film on a pattern including a concave portion formed in a surface of a substrate by repeating a cycle. The cycle includes non-simultaneously performing: (a) forming a first layer by supplying a precursor gas to the substrate; (b) forming an NH-terminated second layer by supplying a hydrogen nitride-based gas to the substrate to nitride the first layer; and (c) modifying a part of the NH termination to an N termination, and maintaining another part of the NH termination as it is without modifying the another part to the N termination by plasma-exciting and supplying a nitrogen gas to the substrate, wherein in (c), an N termination ratio in an upper portion of the concave portion of the pattern is made higher than an N termination ratio in a lower portion of the concave portion of the pattern.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 25, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Katsuyoshi HARADA, Satoshi SHIMAMOTO
  • Publication number: 20180305816
    Abstract: The present invention provides a technique capable of suppressing the formation of particles. The substrate processing apparatus may include: a processing container where a substrate is processed; a process gas supply unit configured to supply a process gas into the processing container; a substrate support installed in the processing container; a first exhaust unit connected to the processing container; a shaft supporting the substrate support; a shaft support configured to support the shaft; an opening disposed at a bottom portion of the processing container and penetrated by the shaft; a flexible bellows disposed between the opening and the shaft support, wherein an inner space of the bellows is in communication with that of the processing container; and a gas supply/exhaust unit configured to supply an inert gas into the inner space of the bellows while exhausting an inner atmosphere of the bellows.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Akira TAKAHASHI
  • Publication number: 20180305817
    Abstract: There is provided a technique that includes: forming a film on a substrate in a process chamber by performing: supplying a precursor gas to the substrate through a first nozzle; and supplying at least one selected from a group consisting of an oxygen-containing gas and a nitrogen-and-hydrogen-containing gas to the substrate through a second nozzle that is configured such that gas stagnation on a surface of the second nozzle caused by the second nozzle is less than gas stagnation on a surface of the first nozzle caused by the first nozzle, or such that contact of the second nozzle with gas staying on the surface of the second nozzle is less than contact of the first nozzle with gas staying on the surface of the first nozzle.
    Type: Application
    Filed: March 19, 2018
    Publication date: October 25, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Shintaro KOGURA, Ryota SASAJIMA, Kosuke TAKAGI
  • Patent number: 10106891
    Abstract: Embodiments of the invention relate to a substrate processing apparatus. In one embodiment, a substrate processing apparatus includes a plurality of process units. The process unit includes a process chamber for processing a substrate, an exhaust conduit connected to the process chamber and an exhaust pump arranged in the path of the exhaust conduit. The substrate processing apparatus further includes a connecting conduit connected to the exhaust conduits of the process units in the upstream of the exhaust pump and a switching unit which switches an exhaust path of the process chamber to the other exhaust pump in the other process unit via the connecting conduit.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: October 23, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Atushi Sano
  • Patent number: 10110253
    Abstract: Provided is a BICM-ID technique which suppresses deterioration of decoding characteristics and reduces a calculation amount. A receiver includes a demodulator, deinterleaver, decoder, and interleaver. The demodulator outputs first extrinsic information by using a received signal encoded and interleaved and a priori information. The deinterleaver processes the first extrinsic information and outputs second extrinsic information. The decoder outputs third extrinsic information by using the second extrinsic information. The interleaver processes the third extrinsic information and outputs fourth extrinsic information. In the receiver that performs iterative decoding processing using the fourth extrinsic information as the a priori information, the demodulator includes a generator, a received signal point candidate narrowing-down unit, and a likelihood calculation unit. The generator generates a plurality of received signal point candidates.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 23, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Keisuke Yamamoto
  • Patent number: 10096463
    Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor from a first nozzle to a substrate and exhausting the precursor from an exhaust port; supplying a first reactant from a second nozzle to the substrate and exhausting the first reactant from the exhaust port; and supplying a second reactant from a third nozzle to the substrate and exhausting the second reactant from the exhaust port. A substrate in-plane film thickness distribution of the film formed on the substrate is controlled by controlling a balance between a flow rate of an inert gas supplied from the second nozzle, a flow rate of an inert gas supplied from the third nozzle, and a flow rate of an inert gas supplied from the first nozzle in supplying the precursor.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 9, 2018
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Yoshitomo Hashimoto, Tatsuru Matsuoka, Masaya Nagato, Ryota Horiike, Shintaro Kogura
  • Patent number: 10096501
    Abstract: A maintenance method of a substrate processing apparatus includes a first processing step of carrying a first substrate holder holding a substrate into a process chamber and processing the substrate held by the first substrate holder within the process chamber, a second processing step of carrying a second substrate holder holding a substrate into the process chamber and processing the substrate held by the second substrate holder within the process chamber, a determination step of determining a replacement timing of the first substrate holder and the second substrate holder, and a maintenance step of, at the replacement timing determined at the determination step, replacing the first substrate holder and the second substrate holder respectively with a third substrate holder and a fourth substrate holder, if at least one of the first substrate holder and the second substrate holder reaches the replacement timing.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: October 9, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventor: Kaori Inoshima
  • Publication number: 20180286727
    Abstract: Described herein is a technique capable of improving the uniformity of device characteristics. According to the technique described herein, there is provided a method of processing a substrate, including: (a) loading a substrate having a patterned hard mask into a process chamber; (b) supplying a metal-containing gas at a first pressure into the process chamber; and (c) supplying an inert gas into the process chamber and storing the metal-containing gas at a second pressure lower than the first pressure after performing (b).
    Type: Application
    Filed: March 9, 2018
    Publication date: October 4, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naofumi OHASHI, Satoshi TAKANO, Kazuyuki TOYODA, Shun MATSUI
  • Publication number: 20180286662
    Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.
    Type: Application
    Filed: March 22, 2018
    Publication date: October 4, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshimasa NAGATOMI, Hirohisa YAMAZAKI
  • Publication number: 20180286725
    Abstract: Described is a technique capable of reducing an effect of a substrate retainer on a substrate processing while maintaining a strength of a substrate retainer. Provided is a substrate retainer configured to support a plurality of substrates in horizontal orientation with an interval therebetween, the substrate retainer including: main support columns; and auxiliary support columns, wherein: each main support columns is provided with a substrate support member configured to support a substrate; a diameter of each of the auxiliary support columns is larger than a diameter of each of the main support columns and smaller than a length of the substrate support member; a distance between an edge of the substrate and each of the auxiliary support columns is shorter than a distance between the edge of the substrate and each of the main support columns; and all of the auxiliary support columns are not in contact with the substrate.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuki NONOMURA, Hirohisa YAMAZAKI
  • Patent number: 10090322
    Abstract: A method of manufacturing a semiconductor device, includes: loading a substrate including a laminated film including an insulating film and a sacrificial film, a channel hole formed in the laminated film, a charge trapping film formed on a surface in the channel hole, a first channel film formed on a surface of the charge trapping film, and a common source line exposed on the bottom of the channel hole; receiving information on a distribution of hole diameter of the channel hole; and forming a second channel film on a surface of the first channel film by supplying a first processing gas and a second processing gas to a center side and an outer peripheral side of the substrate, respectively, so as to correct the distribution of the hole diameter based on the information.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Toshiyuki Kikuchi, Atsushi Moriya, Masanori Nakayama, Takashi Nakagawa
  • Patent number: 10090152
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a seed layer doped with a dopant on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a halogen-based first process gas to the substrate, supplying a non-halogen-based second process gas to the substrate, and supplying a dopant gas to the substrate; and supplying a third process gas to the substrate to form a film on the seed layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 2, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yugo Orihashi, Atsushi Moriya