Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: In a multi-processor system having a plurality of processors connected to each other through a network, a method of executing a program under various environments, includes the steps of transmitting the program from a first processor to a second processor, the first and second processors being included in the plurality of processors, autonomously checking by the second processor whether or not an executing environment set in the program matches to an actual executing environment, autonomously changing the program by the second processor in accordance with the checking result, and executing the changed program by the second processor.

Abstract: A route information input apparatus for specifying a route from an entraining station to an arrival station including a pointing device operated by the user to designate a position on a display screen and a data processing apparatus for executing a data processing in accordance with a program prepared in advance each time the user operates the pointing device to thereby change a displayed content on the display screen. On the basis of positional informations of major stations stored in a first file, a line diagram presented in the simplified form in which truly existing stations are partly omitted and in which the major stations are connected by means of line segments is displayed on a first area of the display screen. A group of station name data omitted from the line diagram displayed on the first area are selectively displayed on a second area of the display screen in the form of a table.

Abstract: A method and apparatus for controlling a conditional branch instruction in a pipeline type data processing apparatus which are adapted to judge whether or not a conditional branch instruction is valid, judge whether or not a condition code necessary for a taken/not-taken judgement made for the conditional branch instruction is valid, and selectively make a taken/not-taken judgement for the conditional branch instruction in accordance with the results of the judgements made to the conditional branch instruction and the condition code.

Abstract: In a one-chip microcomputer, an electrically programmable read only memory (EPROM) is formed together with a read-only memory (ROM) and random access memory (RAM) on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM. In case data are to be written in the EPROM, an EPROM writer is used. This EPROM writer outputs write data to the EPROM and checks (or verifies) the data written in the EPROM immediately thereafter. If any error is detected, a subsequent data write is interrupted. In order to inhibit the unnecessary operation interruption in case the address designated by the EPROM writer comes out of the range of the EPROM, a checking (or verifying) data signal to be fed from the one-chip microcomputer to the EPROM writer is forcibly set at a level which indicates satisfactory operation of the EPROM.

Abstract: A microprocessor including instruction decoding apparatus, instruction execution apparatus and information holding apparatus. The microprocessor performs a first step of storing information specifying the kind of operation to be performed by the instruction execution apparatus, upon execution of a first instruction, in the information holding apparatus and a second step of causing the instruction execution apparatus to perform the kind of operation specified by information stored in the information holding apparatus when a second instruction is decoded and includes information specifying that the operation to be performed by the instruction execution apparatus is the kind of operation specified by the information stored in the information holding apparatus.

Abstract: The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.

Abstract: An information processing apparatus employs a liquid crystal display and a fluorescent lamp for backlighting the screen of the liquid crystal display. A lighting circuit for supplying alternating current lighting power to the fluorescent lamp receives input power from either a commercial alternating current power source or from a direct current battery. The level of the lighting power supplied to the fluorescent lamp is determined based upon a determination of whether the input power is being supplied from the commercial power source or from the battery.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chip 2 and a resin is enlarged by making the external size of a die pad 3 smaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chips 2 having different external sizes can be mounted on the die pad 3 by cutting the leading ends of leads 5 to a suitable length in accordance with the external sizes of the semiconductor chips 2.

Abstract: An information life cycle management system and an information organizing method using the computer system stores information objects composed of a database and program, and a data processing device for processing an information object which is a block of the information in the storage device. Processing and execution of an information object is managed based on information life cycle states, starting with generation of the information object and ending with aborting the information object. An information accessor manager governs the available operation type and area of use of manager information based on the information life cycle state. As information object definition language defines attributes of the information structure and information life cycle state and the managed information object. The information objection is managed in accordance with contents defined by the language.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: When cooling power corresponding to an amount of heat generated by an electronic apparatus can be generated by either n or n+1 cooling units, n+1 cooling units are operated such that each of the cooling units keeps a sufficient margin in reserve. In this manner, even if an abnormality occurs in one of the cooling units, the operation can be continued by the n cooling units. Further, since an operation frequency of a compressor in the cooling unit can be decreased to rotate a motor in the compressor at a lower rotational speed, a speed at which a bearing is worn is slowed, whereby the useful life of the bearing can be prolonged.

Abstract: A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.

Abstract: In a communications system having a plurality of stations interconnected by a two-line circuit, in which the two-line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits; the data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied, while a logic value on the clock bus circuit is fixed. In more detail, the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station, after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state.

Abstract: A microcomputer includes one or more registers therein. These registers are provided for defining a specific address area. When a processor unit in the microcomputer accesses an address in the specific address area, it acknowledges the access to change the bus width and/or bus cycle of the microcomputer dynamically.

Abstract: A data processing system capable of searching for desired data requested by a computer from a memory unit. To obviate a disadvantage that the computer has read data partially including desired data from the memory unit and selected the desired data from the read data, the data processing system is provided with a data processing unit connected to a control unit for controlling a memory unit. Desired data is selected by this data processing unit.

Abstract: In a video signal apparatus, a carrier signal generating circuit includes a VCO for generating a signal having a frequency at least twice that of a carrier signal necessary for conversion to a lower band with a sub-carrier in an NTSC system, a one-half divider circuit for dividing the VCO frequency signal by two, a delayed flip-flop circuit for receiving the divided signal and the sub-carrier signal to generate a difference frequency signal, a 1/40 divider circuit for dividing the Q output, a phase comparator circuit for comparing the phases of the 1/40 divided signal and the horizontal synchronizing signal to output a phase difference, a frequency discriminator circuit for comparing the phase of the flip-flop output with the frequency-divided output of the horizontal synchronizing signal to output a frequency error, and a circuit for converting the output of the phase comparator circuit and the frequency error into DC voltages and applying their sum as a control voltage for the VCO.

Abstract: A method and apparatus for relocating a storage such that a physical address area of the storage, which is allocated to an absolute address area, is replaced with a new physical address area. This relocation process is performed with a Floating Address Register for translating an absolute address into a physical address in a hierarchy storage system including a main storage and a store-in cache memory, thereby reducing a stopping time of the main storage during the relocation process. According to the method, data of the area of object physical addresses to be relocated is fetched into a block of the cache memory, and then the new physical addresses of the storage are allocated to the absolute address to which the old physical addresses have been allocated.