Abstract: An object-oriented data base management system connected to a plurality of data bases includes a class definition unit, a static inheritance processing unit included within the class definition unit, a message processing unit, a dynamic inheritance processing unit included within the message processing unit, and an object management unit. The object-oriented data base management system is of the type that defines the inheritance relationship between a plurality of classes and an arbitrary class and the inheritance priority order, the class being a basic unit of programming, and executes the data processing by solving the inheritance relationship between classes in accordance with the priority order. There is prepared, for each class, updatable inheritance solution status information which the static inheritance processing unit causes to be stored in a table. The inheritance solution status information includes status information and time information.

Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.

Abstract: In a system for data processing by use of a processing language controlled by a job control program for coupling a file having at least one data item to a data set, a method of standardizing data items in an existing program stored in a storage and having a procedure part and a data definition part is disclosed. The names of two data items including the source and destination items of moving in the transfer designated in a plurality of data transfer instructions in an existing program are stored in the storage, and the equivalence number attached to the name of the transfer source item of each of the plurality of data transfer instructions is attached to the name of the transfer destination item. If a plurality of files assigned in the data definition part are defined in a single data set, the file equivalence number is attached to the plurality of files in the storage.

Abstract: The computer aided planning support system of this invention is constructed of a planning information input device from which an object data for making a plan is inputted; an object data storage unit for storing the inputted object data; a planning unit for making a plan by reading the object data stored in the object data storage unit and processing the read-out data in accordance with a planning program; a planning data storage unit for storing the data associated with the plan made by the planning unit; a planning data processing unit for processing the planning data stored in the planning data storage unit in accordance with a predetermined scheduling function and sending the processed data to the planning unit; and a planning information output device for outputting the planning result generated by the planning unit in the form a user can use it.

Abstract: When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks.

Abstract: A problem solving system including apparatus for representing a relationship between a goal including subgoals and its lower level subgoals and for achieving the goal as a strategy of a first kind. Apparatus is provided for repetitively dividing a goal including subgoals into its lower level subgoals according to the relationship between the goal and the subgoals. A strategy of a second kind is used to specify the functions to be performed by the apparatus to achieve the lowest subgoal. Apparatus is also provided for simplifying and solving a complicated problem by executing the goal including subgoals by use of the strategies of the first and second kinds.

Abstract: When a current that flows into a power output element is greater than a predetermined value, pulse width-modulated signals are formed which vary in inverse proportion to the current value in order to drive the power output element. When an excess current flows into the power output element, therefore, the power output element is allowed to intermittently operate for only short periods of time, and the current can be decreased during the current-limiting operation.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection.

Abstract: Task execution control for a multiprocessor wherein at a time point when a post issue task ends the use of a shared resource, the shared resource is released, another task which is running on another processor is allowed to lock the shared resource, and thereafter the task is made ready. After that, the post procedure is initiated, and thereafter through the high-speed dispatch procedure, the processor is granted first to a task which has failed to lock the shared resource, and the task is prompted to retry to lock the shared resource.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: With respect to input/output requests; a microprogram controls collection of data according to the data format; data accessing divides the requests for every recording medium and performs asynchronous processing; an on-line process is carried out in view of the processing priority order of the requests; parallel accessing sets requests for each medium; buffer control assures a block buffer and a page address list before receiving requests; data accessing sets a list of CCHHR codes in response to a continuous characteristic of the stored state in the recording medium; and mode deciding judges the two data transfer modes, a page search mode and a data search mode, in response to the requests.

Abstract: An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In response to an output request from a HOST system to the disc systems, data outputted from the latter are stored in the storage areas of the cache memory. The data stored in the storage areas and outputted therefrom in response to the output request are transferred to the disc systems. The storage areas storing the data requested and not yet stored in the disc systems are grouped correspondingly to the disc systems where the output data are to be stored. The resulting group is managed as a first attribute group. Write-after processing for every disc units can be executed in parallel efficiently without involving high processing overhead.

Abstract: Disclosed is a resin-molded type semiconductor device having a thin package while avoiding short-circuit of wires with a common inner lead. In the construction thereof, a common inner lead constituted by a thin metal sheet is fixed onto a circuit-forming surface of a rectangular semiconductor chip substantially in parallel with longer sides of the chip and substantially in a central region of the chip, and a plurality of inner leads for signals, which are in the form of a frame, are stacked and fixed onto the common inner lead; then these components are molded with resin.

Abstract: In a method for determining an optimum scheduling in a computer-aided scheduling system the data associated with a schedule to be generated is previously stored in a memory data. A strategy decision table showing therein one or more scheduling strategies suitable for a plurality of the states in a scheduling process is prepared. An optimization definition table indicating degree of improvement precedence or precedence order of the scheduling strategies of the evaluation items, where degree of improvement precedence is defined as degree of improvement of evaluation value of he evaluation item in changing of the scheduled strategy, is prepared. A schedule is generated by repetition of selecting and executing the scheduling strategies by using the strategy decision table. The other schedules are generated by changing the scheduling strategy selected in the state of the scheduling process by using the optimization definition table. An optimum schedule having the best evaluation value is selected.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: A digital timer unit employs a capture register and a save register. The capture register latches count data provided from a counter in accordance with a first edge of an event pulse. The save register latches count data of the capture register in accordance with a second edge of the event pulse while the capture register latches new count data provided from the timer. Data within the capture register and the save register after completion of the event pulse define a duration of an event pulse with a relatively small duration.

Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.

Abstract: A computer aided text generation system and method provides functions of aiding a logical outline structure of a text, aiding the text generation using a conventional expression, aiding the text generation without using conventional expression, aiding the refinement of the generated text and aiding the collection of illustrative sentences. The present system permits generation of a finished text of high quality.

Abstract: A switching system is provided in which when a calling subscriber has transmitted an identification (ID) number of a called subscriber and an ID number of the calling subscriber from a calling terminal to a switching equipment having a subscriber control table at the time of making a call, the switching equipment receives the ID numbers and connects the calling terminal with the called terminal.