Abstract: A cache memory wherein data words identified by odd address numbers are stored separately from data words identified by even address numbers. A group of diagnostic control registers supply signals for controlling the testing of the cache within the cache memory to determine the operability of the individual elements included in the cache memory.

Abstract: A data processor performs a decimal multiply operation using apparatus including a register for storing multiplier decimal digits, a register for storing a multiplicand operand of decimal digits, a register for storing partial products and arithmetic logic units, and a read only memory for storing the units and tens product digits. The multiplier digit and a selected multiplicand digit are applied to the address terminals of the read only memory. On successive cycles, the units product digit and the tens product digit are added respectively to selected partial product digits and the sum replaces the selected partial product digits.

Abstract: In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.

Abstract: A banking system is disclosed which comprises a central computer system in electrical communication with remote automated teller machines, wherein the architecture of the banking system is such that the likelihood of a security penetration is substantially decreased whether the automated teller machine operates in an on-line or in an off-line mode.

Abstract: A cathode ray tube display terminal includes a pluggable power supply. A recessed handle for removing the power supply from the CRT terminal is trapped by the AC line cord plug necessitating removal of the plug to permit access to the handle.

Abstract: A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage locations, the contents of the second multiplicity of storage locations adapted for addressing the first multiplicity of storage locations, a counter for addressing the second multiplicity of storage locations; and control logic for controlling the counter and entry and withdrawal of data signals in the first and second multiplicity of storage locations.

Abstract: Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals together with associated parity bits for writing into an addressed storage location of memory. During the write cycle, error encoder circuits generate check code bits from the multibyte data and parity bits which are coded to signal selectively the presence of a multibyte uncorrectable error condition in accordance with the parity bits from a device. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check bits read out from an addressed location are operative to generate a number of syndrome bits.

Abstract: A cathode ray tube display terminal includes a printed circuit logic board permanently mounted in a molded plastic enclosure assembly during "on the shelf" storage and shipment of the enclosure as a spare part and during normal operation of the CRT display terminal. The enclosure assembly includes a top portion and a lower portion which snap together. The printed circuit logic board is assembled between the upper and lower portions of the enclosure which are secured by a single screw. A snap-out section allows replacement of a read only memory on the logic board.

Abstract: In a data processing system which includes a central processing unit and one or more main memory units comprised of semiconductor dynamic random access memory chips, logic is provided within the system to provide for the single stepping of the central processing unit clock thereby allowing for the execution of one CPU cycle. The system logic is organized such that the memory refresh command signals, which are normally generated by the CPU, are generated by the single step logic thereby maintaining the contents of the main memory modules. The logic of the overall data processing system is organized such that most transfers of information between the main memory, the CPU and I/O controllers, to which peripheral devices are connected, may take place in the single step mode of operation without the loss of information.

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer which polls the devices in a predetermined order. Apparatus in the communication controller rearranges the polling order to provide highest priority to an input/output device in a receive mode that is currently operative and to give lowest priority to an input/output device in a transmit mode that has just completed its operation.

Abstract: A commercial instruction processor executes decimal arithmetic instructions on string decimal and packed decimal operands. A read only memory is responsive to control signals generated from the operation code portion of the instruction, a type signal from a descriptor word of the instruction, and signals indicating the present decimal digit position being processed to generate signals indicating next decimal digit position to be processed.

Abstract: An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match.

Abstract: A logic system is provided in a video system for accommodating the display of video data characters and the application of visual attributes to such characters whether occurring singularly or in fields.

Abstract: An intersystem communication control system in an intersystem link (ISL) unit is provided to accommodate the simultaneous bidirectional transfer of binary coded information between communication busses in a data processing system, wherein the plural communication busses are electrically interconnected by ISL unit twins, and information may be transferred between plural communication busses asynchronously.

Abstract: A logic control system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein information may be transferred between plural communication busses while further information flow continues on each communication bus at the bus rate, and additional information transfers between the communication busses continue to be handled by the ISL unit.

Abstract: A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character.

Abstract: An article of furniture used to support a computer terminal or a similar object having means to continuously adjust in a stepless fashion the table top height through the operation of a single operating lever located just beneath the table top which can be operated from a seated or standing position. Swinging the operating lever in one direction in the horizontal plane releases an adjustable length gas spring controlling table top height, allowing for the raising or lowering of the table top which is followed by the return of the operating lever to its original position which locks gas spring at its new length and rigidly locks the table top at its adjusted height.

Abstract: The method of mounting on a substrate an integrated circuit (I.C.) chip having flexible beam leads bonded to input/output (I/O) terminals on the active face of the I.C. chip. The substrate has a chip pad and outer lead (OL) pads associated with the chip pad on a surface of the substrate. Preforms of a fiber glass web coated with a thermosetting plastic are cut to a size that substantially conforms to that of the chip pad. The substrate and the chip pad are heated to a first temperature which the preform will adhere to the chip site, the preform is placed on the chip pad, and the active face of the I.C. chip is pressed into the preform. The temperature of the substrate, preform and chip, are then raised to a second temperature higher than the first to partially cure the thermoplastic material and to encapsulate the active face of the I.C. chip and portions of the leads proximate the chip in the thermoplastic material of the preform. The I.C.

Abstract: An apparatus and method for decoding input signals on four lines to produce an outgoing information stream of binary bits.