Abstract: A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.

Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.Two, three state busses are employed. The first, three-state data bus is used to transmit memory data to the error detection and correction (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state data transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.

Abstract: Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Abstract: Direct connect devices such as cathode ray tube displays are coupled to a communications controller through a long cable and a flexible line adapter package. Apparatus in the controller generates a clocking signal which is applied to a Universal Synchronous Receiver Transmitter (USRT) and to the direct connect device. The USRT receives data from a microprocessor and transmits a stream of data signals synchronized to the clocking signal. The data signals and the clocking signals are received by the direct connect device. The clocking signals strobe the data signals approximately in the center of a data pulse since transmission delays for the data signals and the clocking signals are approximately equal.

Abstract: A system for transferring substantially identical fixtures, on each of which is mounted a workpiece, from a stack of said fixtures in a transferor magazine to a transferee magazine. Each of the magazines has substantially planar walls defining a prismatic interior space having a substantially rectangular cross-section and open top and bottom, or end, faces. The walls of the magazine are provided with spring catches for retaining in the storage space fixtures placed therein, with the catches defining that portion of the interior of the magazine constituting a fixture storage space. The transferor magazine is mounted on a transferor base, which is provided with a transferor station and apparatus for placing the catches of the transferor base in a condition so that fixtures in the storage space can descend into the transferor station. The transferee magazine is mounted on a transferee base which is provided with a transferee station.

Abstract: A data processing system includes a number of input/output devices coupled to a communication multiplexer by 1 synchronous communication line and a number of asynchronous communication lines. During the polling operation, receive communication lines have high priority and transmit communication lines have low priority. Apparatus in the polling logic gives the synchronous communication line in the receive mode first priority and the synchronous communication line in the transmit mode second priority.

Abstract: An apparatus for conducting input output operations with another data processing device in a flexible and low cost manner is comprised of a programmed microprocessor coupled to a keyboard, a parallel port, and a modem. The microprocessor is programmed to periodically scan the keyboard to determine what keys if any are depressed. It also scans the parallel port for incoming data and senses incoming data from the modem by sensing a start bit. Control characters from the keyboard can set options such that incoming data from an input can be simultaneously sent out from the modem and/or parallel port.

Abstract: A data processing system having a communications subsystem operating in a byte control protocol mode includes apparatus for establishing byte synchronization between the data circuit terminating equipment (DCE) and the communications subsystem. The apparatus includes a flop for receiving a stream of predetermined binary bits, a counter generating count signals indicative of the number of binary bits between a byte timing signal from the DCE and the last binary ONE bit of the last byte containing all binary ONE bits, a shift register for the serial shifting of the transmitted data bits and a multiplexer responsive to the count signals for selecting the shift register terminal, thereby timing the byte timing signal to the binary bit stream of data bits, including bytes of all binary ONE bits and a byte of all binary ZERO bits, followed by bytes of data bits.

Abstract: A multiprocessor system comprising a plurality of processors and a memory unit which are connected through a common bus whereby each processor communicates with the memory through the bus. Communication among processors is effected by storing in a plurality of memory zones the messages intended for the several processors. The memory zones are each dedicated to one processors, but are accessible to all the processors. The communication among processors is performed by sending a notify signal on the common bus which is identified only by the processor for which it is intended. The notify signal is acknowledged by the notified processor without interrupting its ongoing operation. The notified processor subsequently accesses the memory unit and reads the message in the appropriate memory zone.

Abstract: A switching regulator power supply operates at a variable high frequency with low power dissipation and a minimum of complexity. The transformer primary windings are included as part of a self starting circuit which starts a pulse generator having a fixed pulse width and variable frequency. During a first cycle of operation, the self starting circuit in response to the input rectified AC power after a predetermined period of time applies sufficient voltage which enables the pulse generator to begin generating a first output pulse of fixed pulse width. This causes the primary windings to store energy and feedback energy to the self starting circuit which increases the voltage applied to the generator causing it to begin normal operation at maximum frequency.

Abstract: An electrographic printhead and a process for assembling same that results in decreased shorting between styli and increased resistance to wear from paper abrasion and further provides high resolution electrographic printing. Each electric circuit board forming the electrographic printhead comprises arrays of wires that are bonded between two stainless steel support bars utilizing an alumina treated face for insulation and molybdenum face for wear resistance.

Abstract: This relates to a fiber optics communication link, wherein a single optical fiber carries data bi-directionally between two computers. The first computer is coupled by means of control logic to a first transmitter and a first receiver. The first transmitter and receiver are in turn coupled to a single optical fiber by means of a Y-coupler. A second computer is similarly coupled via control logic to a second transmitter and second receiver, which is in turn coupled to the single optical fiber by means of a second Y-coupler. To minimize problems due to reflections, each receiver is disabled when its corresponding transmitter is transmitting data.

Abstract: A logic system is provided in a video system for accommodating the display of both video data characters and graphic characters, and the application of visual attributes to such characters whether occurring singularly or in fields.

Abstract: A writeable control store in a data processing system is provided with a dual mode capability. Coupled with the control store in the system is a central processing unit which may provide the next address of the control store's memory dependent upon the mode of the control store. Otherwise, also dependent upon such mode, the control store memory is addressed, dependent upon the results of tests conducted in the central processing unit, by one of at least two alternative addresses. The control words addressed in the writeable control store are used to control the operation of the central processing unit.

Abstract: An integrated circuit package in which an integrated circuit chip having flexible beam leads, the inner lead bonding sites of which are bonded to input and output terminals on the active face of the chip, is mounted active face down on the top surface of a substrate. The top surface of the substrate is provided with a chip pad on which the integrated circuit chip is mounted and outer lead pads. The back surface of the substrate has a heat sink pad which is positioned substantially opposite the chip pad. A plurality of thermal passages is formed through the substrate interconnecting the chip pad and the heat sink pad. A good thermally conductive material fills the passages. A preform comprising a segment of fiber glass web coated with a thermosetting and thermally conductive plastic is positioned on each chip pad between the chip pad and the active face of the integrated circuit chip.

Abstract: A long term response enhancement for a digital phase-locked loop is implemented to provide a relatively minor change in the phase of the output signal over a relatively long period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur between successive input signals, producing an output signal when the two numbers agree.

Abstract: A logic system is provided in a video system for accommodating the display of both video data characters and graphic characters.

Abstract: A communications subsystem having a microprocessor coupled to an address bus and a data bus includes a latching register also coupled to the address bus and the data bus. The latching register is responsive to signals from the data bus and address bus for storing bits representative of a direct connect mode, a clear to send mode, and a bit oriented or byte control protocol mode.