Abstract: A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.

Abstract: A cache clearing apparatus for a multiprocessor data processing system having a cache unit and a duplicate directory associated with each processor. The duplicate directory, which reflects the contents of the cache directory within its associated cache unit, and the cache directory are connected through a system controller unit. Commands affecting information segments within the main memory are transferred by the system controller unit to each of the duplicate directories to determine if the information segment affected is stored in the cache memory of its associated cache memory. If the information segment is stored therein the duplicate directory issues a clear command through the system controller to clear the information segment from the associated cache unit.

Abstract: A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a number of memory modules. Each controller also includes reconfiguration apparatus for enabling reconfiguration of the memory system upon detection of a fault. The reconfiguration apparatus includes apparatus for identifying the type and design revision of the controller associated therewith enabling more expeditious fault diagnosis based upon status signals provided by the controller during diagnostic testing by the central processing unit.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.

Abstract: The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.

Abstract: A microprogrammed commercial instruction processor (CIP) is placed in a stall mode during the transfer of information between the CIP and main memory by stalling a free running clock signal. When the transfer of information is completed, the free running clock cycles. If main memory indicates an error condition, then the free running clock signal is again stalled after one cycle to allow the firmware in the CIP to process the error.

Abstract: A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

Abstract: A logical control system is provided for accommodating both single and double byte accesses to a video terminal system display memory to supply video character and visual attribute data to a video screen without limiting the quantity of visual attributes and without the needless occupation of video screen character positions by visual attribute characters.

Abstract: A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

Abstract: A switching regulator power supply operates at a variable high frequency with low power dissipation and a minimum of complexity. The transformer primary windings are included as part of a self-starting circuit which starts a pulse generator having a fixed frequency and variable pulse width. The self-starting circuit includes a control circuit network which connects to the transformer primary windings and a low voltage regulator circuit connects to the pulse generator and network. The control circuit network provides the voltage regulator circuit with the desired current characteristics of high instantaneous current during a short turn-on time interval and a zero current during power supply operation. The self-starting circuit in response to the input rectified AC power after the short turn-on period of time applies sufficient voltage which enables the pulse generator to begin generating a first output pulse.

Abstract: A switching regulator power supply operates at a variable high frequency and pulse width with low power dissipation and a minimum of complexity. The transformer primary windings which are included as part of a self starting circuit start a pulse generator having a variable pulse width and variable frequency. During operation, the input RC network of the pulse generator, in response to the input rectified AC line voltage, conditions the pulse generator to generate output pulses whose widths vary as a function of changes in the input rectified AC voltge. An error circuit coupled to the secondary winding compares the output DC supply voltage to a reference voltage and generates an error signal which is applied through a coupling circuit for further adjusting the frequency of the pulse generator within a desired range to existing load conditions.

Abstract: A hardware monitor interface unit (HMIU) is coupled to a data processing system. Programmable hit matrices (PHM's) in the HMIU store information which is compared with information from the data processing system. The PHM's generate "hit" signals indicating comparison. These "hit" signals are received by monitors coupled to the HMIU which are used to compile the data processing system performance data. Appartus in the HMIU generates clocking signals enabling the information to be received by the HMIU and generates strobing signals to be used for timing the "hit" signals and other control signals received by the monitors.

Abstract: One or more common buses are provided for coupling a plurality of units in a data processing system for transfer of information therebetween. The central processing unit (CPU) allocates the one or more common buses to one of the requesting units as a function of request type and on which of one or more common buses the requesting unit is located. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the one or more common buses.

Abstract: A communications controller of a data processing system uses a microprocessor to control communication operations. Apparatus in the controller stretches the microprocessor clock cycle signals for selected operations to allow the microprocessor speed to match the speed of the logic performing the selected operation. The apparatus includes a counter which is freerunning for the stretched cycle and reset on a predetermined cycle for the "no stretch" cycle. A decoder coupled to the counter conditions logic gates to generate the microprocessor clock cycle signals.

Abstract: A stepping motor drive circuit having pairs of magnetically coupled phase windings (1, 3 and 2, 4), comprises current chopping control circuits (23, 24) for controlling the on/off switching of a plurality of driving transistors (5, 6, 7, 8) each coupled to a respective phase winding, and the circuits associated with each switching transistor for reducing their storage times and hence switching losses. More particularly, with reference to the switching transistor (5), the related circuit for storage time reduction comprises a series connected capacitor (25) and a diode (45). The circuit connects between one terminal of one winding (2) of the pair of phase windings which is magnetically coupled to the one winding (1) of the other pair connected to such switching transistor (5) and to the base of such transistor (5). As soon as the transistor (5) is caused to switch from ON to OFF, the circuit applies a reverse voltage pulse to the base of the transistor (5) causing a fast transition towards the cutoff region.

Abstract: A data processing system includes a number of subsystems, all coupled in common to a system bus. Also coupled to the system bus is a hardware monitor interface unit (HMIU) for receiving all information transferred between subsystems. The HMIU includes programmable hit matrices (PHM's). The PHM's include memory circuits which generate "hit" signals when predetermined information addresses the memory circuits. The "hit" signals or binary ONE's are loaded into the memory circuits during a load mode during which system bus information specifically addressing the HMIU is received on two system bus cycles for each address location of the memory circuit. The data bus contains the memory circuit address during the first system bus cycle and the data during the second data bus cycle. An address bus signal identifies the cycle.

Abstract: A data processing system including a control store for storing a microprogram constituted by a number of microinstructions, first and second control processors connected in dual fashion for processing data at the same time under control of the microprogram and a cache memory for storing a part of data stored in a main memory. The system compares micro-addresses from the first and second control processors and combines the micro-addresses to form one micro-address and supplies the micro-address to the control store.

Abstract: In combination with a host processor CPU, means are provided to a standard computer terminal keyboard to reconfigure an identity change of the keyboard for another use/uses and to identify its new configuration, status and other vital information to the host CPU.

Abstract: This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.