Abstract: A sequencer control for controlling the time sequencing of the energization of controlled elements includes a microprocessor unit. A large number of input lines and output lines are uniquely multiplexed into a relatively small number of I/O terminals on the microprocessor. The multiplexing, the sequencing and all of the delays are effectively controlled by the microprocessor.

Abstract: Apparatus and method for performing a logical not function in a multi-compare environment is disclosed. By performing two equivalence compares of a measured variable against selectable target values and using the result of the equivalence compares to selectivity set or reset a bistable element, the need for inverting and multiplexing the output of a comparator that is otherwise required when performing a NOT equivalence function in a single-compare environment is eliminated. The not function logic is used in a system analyzer connected to a data processing system and is used to selectively enable the tracing of software execution as a function of whether or not a variable is a predefined value.

Abstract: A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

Abstract: A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.

Abstract: A microprogrammed commercial instruction processor in a data processing system includes a bank of switches coupled to a multitapped delay line for selecting delay line signals for setting the basic clock timing. Another of the switches when activated conditions the commercial instruction processor so that when it is reset a special clock setting firmware loop is entered. The loop provides an uninterrupted succession of clock pulses which allows one to adjust the basic clock timing within specification.

Abstract: A microprogrammed control unit with multiple branch capability comprises in addition to a control memory, a first auxiliary read/write memory (21) having low parallelism and a second auxiliary read/write memory (30) having high parallelism. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions (JC1, JC2, JC3) to be examined and jump addresses (JA1, JA2, JA3) and extends the information contained in the microinstruction read out from control memory.Thus it is possible to associate jump (or branch) microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them.

Abstract: Apparatus adjusts the low supply voltage applied to the bipolar gate array circuits of a semiconductor chip to provide uniform propagation delay in the signals operated on by the array circuits notwithstanding variations in manufacturing tolerances and temperature variations. The apparatus includes a voltage regulator circuit and a first resistor located off the chip connected between its output and adjustment terminals and a second resistor located on the chip connected to the adjustment terminal of the regulator circuit. The voltage regulator circuit in response to changes in the resistance of the second resistor adjusts the low supply voltage at its output terminal so as to provide uniform signal delays through the array circuits.

Abstract: A cache memory including an even data store for storing data words associated with even address numbers and an odd data store for storing data words associated with odd address numbers, a local bus for transferring a low order data word and a high order data word simultaneously from the cache memory to a system element requesting the transfer of a pair of data words through the supplying of a single address number request, and a data steering multiplexer for supplying the data word associated with the memory request number, as outputted from either the odd or even cache data store to the low order data word transfer portion of the local bus and the other of the pair of data words outputted from the odd or even data store to the high order data word transfer portion of the local bus.

Abstract: An electrographic printhead and a process for assembling same that results in decreased shorting between styli and increased resistance to wear from paper abrasion and further provides high resolution electrographic printing. Each electric circuit board forming the electrographic printhead comprises arrays of wires that are bonded between two stainless steel support bars utilizing an alumina treated face for insulation and molybdenum face for wear resistance.

Abstract: The present invention relates to a power sequence device which comprises an element which generates a sequencing code which is capable of being decoded by actuators included in the various equipment cabinets. The sequencing code is initiated by a sensing element which indicates the input power has reached a stable threshold whereupon the various cabinets comprising the data processing system are turned on in a desired order. Upon loss of power, the sensing element generates a warning signal indicating an impending power loss thereby enabling the equipment to perform an orderly halt.

Abstract: A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal.

Abstract: A monitor interface unit couples a monitor to a data processing system which includes a central processing unit (CPU). The monitor generates data for determining the performance of the data processing unit. The monitor interface unit includes apparatus for stopping the CPU clock during a particular CPU operation and then slowing down the CPU clock rate.

Abstract: An integrated circuit package in which integrated circuit (I.C.) chips having flexible beam leads, the inner lead bond sites of which are bonded to input/output (I/O) terminals on the active faces of the chips, are mounted active face down on a surface of a substrate. The surface of the substrate is provided with chip sites and outer lead (OL) pads associated with each chip site. A preform of a fiber glass web coated with a thermosetting plastic is positioned on each chip site between a chip site and the active face of the I.C. chip. The plastic material of the preforms encapsulates the active faces of the chips, including a portion of each of the leads proximate a chip, and secures each chip to its chip site. The outer lead bond sites of the leads are bonded to OL pads of the substrate with the exposed portions of the leads between the OL pads and the encapsulated portion being bent away from the substrate and under compression.

Abstract: A technique and apparatus for storing data and addressing stored data in a memory from which multiple words of data are to be retrieved in parallel is disclosed. The memory is addressed by providing the address of the first of N consecutive words to be retrieved in parallel. The data is stored in memory in physical data words which contain N logical data words such that the addressing of one physical data word will result in N logical data words being read in parallel from the memory. Each physical data word contains the contents of the logical data word having the same address as that of the physical data word in its leftmost position followed in the next right position by the contents of the logical data word having the next higher address, and so on until the rightmost position of the physical data word contains the contents of the logical data word with an address equal to the physical data word address plus N-1.

Abstract: An electromagnet assembly for a matrix printing head which can be automatically assembled and a manufacturing process for automatically assembly said electromagnet assembly.

Abstract: A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

Abstract: A time accounting system for accounting for the time a process spends in a ready state, a wait state, or a running state. The system includes a time-of-day clock coupled to a central processing unit for outputting the time-of-day whenever a process changes state. A memory also coupled to the central processing unit stores the contents of a plurality of addressable process control blocks and each process control block includes first, second, and third storage locations for storing indications of the amount of time an associated process has been in the running, ready, and wait states, respectively. The central processor unit accesses the process control blocks and updates the process times stored therein in accordance with control signals generated by decoding a string of microinstructions stored in a control store memory. The time-of-day clock is accessed each time a process enters one of the running, ready, or wait states and each time the execution of a process is completed.

Abstract: Use of a control storage device coupled with a central processing unit is locked, during the loading process from the unit to the device, to a would-be user of the device until such loading process is complete as indicated by a so-called "unlock" command received from the central processing unit. An indication of an error or malfunction in the control storage device either during the loading process or thereafter is also provided to the central processing unit.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: Step motor control circuit of the "current chopping" type where, according to the required operative conditions, both the energization current level and the "chopping" frequency is varied. When the current level applied to the motor phases is high, a relatively low chopping frequency is used and, on the contrary, when the current level is low a relatively high chopping frequency is used. Particularly, this allows the use of chopping ultrasonic frequency for the holding operative condition of the motor, where a low energization current level suffices, without causing unacceptable power losses in the current switching components. This has the advantage of eliminating under such condition, the motor noise due to the pulsating electrodynamic actions to which the motor is subjected.