Abstract: Sequencer means for a microprogrammed control unit which develops consecutive addresses of microprograms, branches to subroutines with address saving and possible return to microprogram, as well as interrupting microprogram forcings with address saving of the interrupted microprograms.In order to allow the double saving of microprogram and subroutine addresses in case of concurrent interruptions and branches, the sequencer means is provided with two address generation loops each including a register. The two loops have a common portion to which they accede through a multiplexer. The first loop is further coupled to a saving register stack.While the first loop executes the saving of a microprogram address and the latching or a branch address received from the second loop, the second loop executes a first updating and related latching or interrupting microprogram address.

Abstract: A data processing system which includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal, as well as the length and position of the most significant decimal digit in a main memory word, are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory, high order word first or low order word first, the number of double words in the operand and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor.

Abstract: A data processing system includes a central processing subsystem, a main memory subsystem, and a number of peripheral subsystems including a communication subsystem all coupled in common to a system bus. Subsystems communicate with each other during asynchronously generated information bus transfer cycles. Each one of the subsystems receives information by providing any one of three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for an extended period of time, and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

Abstract: A reader/sorter reads documents which include MICR, OMR and OCR encoded characters. The reader/sorter reads each type of character sequentially at separate read head positions. Character codes read by a particular head address a separate area of address locations in a random access memory which stores equivalent character codes which are used by the data processing system. The random access memory is loaded with the translated character codes, allowing a data processing system to communicate with the reader/sorter.

Abstract: A cache memory for use in a data processing system wherein data words identified by even address numbers are stored separately from data words associated with odd address numbers to enable the simultaneous transfer of two successively addressed data words to or from the cache memory by the transferring of a data word associated with an odd address number and a data word associated with an even address number.

Abstract: Apparatus for entering encoded data, command, and address information via a keyboard for transfer to an automated maintenance system designed to perform certain tests on or cause selected events in a unit of a data processing system such as the central processing unit. The data, command and address information entered via the keyboard by an operator serves to control the tests performed by or the events caused by the automated maintenance system. The maintenance panel also includes a plurality of display devices for displaying the data, command and address information sent to the automated maintenance system as well as data received by the automated maintenance system from the unit under test indicating the correctness of its performance. In the preferred embodiment, several LED indicators are also used for prompting and status indication.

Abstract: A data processing system includes a commercial instruction processor (CIP) for executing decimal arithmetic instructions. The operands processed by the CIP include packed decimal and string decimal operands. The decimal arithmetic instruction includes descriptors for describing the characteristics of the operands. A register coupled to an arithmetic logic unit stores double words of the operands which are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory. The read only memory output write signals select the decimal digit, byte or double word positions of the register for writing.

Abstract: A paging apparatus for improved mapping of virtual addresses to real addresses, addressing physical devices coupled to various communication buses, and controlling flow of data. By means of an eight-bit addressing apparatus activated for certain instructions which normally can address only 256 locations, an additional 512 locations can typically be addressed by generating control signals to modify a virtual address into a real address capable of addressing the additional locations. Additionally, the apparatus can control flow of data by enabling or disabling data control apparatus.

Abstract: A logic memory control system for accommodating plural read/write requests to a video terminal display memory is provided without the need for multiplexing common busses shared by the video terminal logic devices accessing the display memory, or for compromising video terminal data transfer rates.

Abstract: A data processing system operating in a bit oriented protocol (BOP) mode of operation senses a transmit underrun; that is, the subsystem is not receiving data from a microprocessor fast enough to maintain the synchronous transmission over the communication line. Apparatus senses the transmit underrun state and generates an abort sequence of bits containing from 8 to 13 successive binary ONE bits.

Abstract: A system comprising several peripheral microprocessors are connected to a central processor through a common bus. Each processor may access the bus using an interrupt signal. In order to avoid conflicts among processors in accessing the bus, processors are designated with decreasing priority. A processor which accesses the bus by using said interrupt signal generates at the same time an inhibit signal which prevents processors having a lower priority from emitting a said interrupt signal. In order to reduce the propagation time, a bypass network for the inhibit signal is associated with each processor and a propagation path is provided for the inhibit signal in the form of a matrix.

Abstract: Each row of video information in a display memory includes a linking character code followed by address codes representative of the address location in such display memory of a first data character of a next row of video information displayed on the CRT screen. Both row insertions and deletions may be accommodated by changing address codes under firmware control without requiring the complete rewrite of video information stored in the display memory.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a first delay line coupled to an inverter by using a multitapped second delay line to delay the rectangular wave train by selectable predetermined period. A control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to the rectangular wave train clock cycle period plus the period of the second selected predetermined delay. By serially connecting a multitapped third delay line in series with the second delay line and by providing a first switch to select one of the outputs from said third delay line, the clock cycle period of the clock system may be adjusted.

Abstract: The present invention relates to a power supply which includes a switching regulator and an over-current detector, having a reference circuit for providing an over-current threshold level. A means is provided by the present invention for adjusting the over-current threshold level without interrupting the system by utilizing a switch to provide an inhibit signal to a fault shut down circuit and for inserting a component into the reference circuit to modify the over-current threshold level to the desired adjustment level.

Abstract: A transport system for transporting fixtures adapted to hold a workpiece sequentially from a fixture transferor station to a fixture transferee station. A fixture guide rail interconnects the two stations and is provided with a chain guide recess that extends from one station to the other. A continuous plastic timing chain cable is mounted on a plurality of sprockets so that the chain can be made to rotate. The sprockets are positioned so that the timing chain is positioned in the chain guide recess. Drive pins are mounted in selected ones of the links of the chain so that the pins will project from one side of the chain. The drive pins initially contact a fixture positioned in the transferee station and move each fixture, in turn, along the guide rails to the transferee station. A drive motor is connected to one of the sprockets to cause the sprocket to move the chain. The distance between drive pins is substantially constant and greater than the corresponding dimension of the fixtures being transported.

Abstract: A microprogrammed controlled commercial instruction processor coupled to a common bus executes a diagnostic microprogram to check the data path of the common bus interface registers and their associated internal registers. Decoded bits of a predetermined microword of the diagnostic microprogram generate a signal which transfers a predetermined data word containing a plurality of bytes stored in a first of the internal registers sequentially through the interface registers to a second of the internal registers during one microword cycle. Apparatus generates bad parity for selected bytes. Subsequent microwords compare the contents of the first and second internal registers and verify the detection of the "bad" parity.

Abstract: A serial printer is disclosed where the printing is performed by a printing head (22) mounted on a carriage (21) movable along the printing line, a transparent leaf (36) mounted on the carriage presses the printing support (25) (paper) against a platen (24) around the zone where the impression is performed thus considerably reducing the noise and vibration generated by the printing support vibrations during the printing.Preferably, the leaf is provided with a window (45) wherein the impression is performed in order to press the printing support against the platen all around the print zone. As the leaf is transparent, it does not preclude the visibility of what is printed. Besides, as the leaf is mounted on the carriage, when the carriage is in its travel position, the leaf does not interfere with the loading of the printing support in the printer.