Abstract: A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element and the second element. The apparatus comprises a shaft, having a first, second, and third diameter along the axis of the shaft, thereby forming a first, second, and third shaft, respectively, the first diameter being the smallest diameter and the third diameter being the largest diameter. The first shaft is threaded, for mating with the second element. A spring, having an inside diameter smaller than the diameter of the third shaft and having a length approximately equal to the length of the first and second shaft is coaxially positioned over the first and second shaft.

Abstract: A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

Abstract: A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.

Abstract: A pair of conductive ground clips each having a plurality of flexible fingers, are slid into an interference engagement with the ends of a flange of a D-shell connector. The ground clip equipped connector is held in a plastic connector housing which is latched to a conductive plate by flexible latching arms that are a part of the connector housing. As the connector housing is latched to the plate with the latching arms, flexible fingers on the clips touch the plate and flex making and maintaining a good electrical connection therewith. The ground clips maintain a proper electrical ground connection between the housing contained connector and the plate avoiding undesirable electrostatic discharge, electromagnetic interference, and radio-frequency interference.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.

Abstract: An electronic system is packaged to provide a single etched backplane. Bus bars are physically fastened to bushings which are soldered to the backplane power etch lines to provide power to the system.Printed circuit boards are plugged into connectors mounted on the backplane for receiving power and transferring logic signals between printed circuit boards. A number of power supplies are plugged into connectors mounted on the bus bars for transmitting power, and plugged into connectors for transferring logic signals.

Abstract: A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.

Abstract: A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the register to control the merging of the identified zone or zones of the associated word with the remainder of the data in the addressed word block.

Abstract: A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.

Abstract: A digital apparatus recovers data recorded in FM or MFM on a magnetic media moving at a normal speed in which the reading of the media provides a sequence of timing/data pulses at variable intervals, which differ from a nominal interval due to speed error and magnetic "peak-shift". The apparatus provides identification of a nominal interval between read out pulses and the reconstruction of a correct stream of pulses properly located within a window signal. It includes a digital measurement unit which at each read out pulse n received in input supplies at an output a code indicative of the actual duration of the interval N between the pulse n and a previous pulse n-1; and a speed correction unit which corrects the measured duration of the interval N relative to speed error detected by the digital measurement unit during reading of a synchronization bit field.

Abstract: Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.

Abstract: A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.

Abstract: A squeegee is utilized in a screen process printer for microcircuits and components thereof. The type is one in which the squeegee and a flat stationary screen are mounted with the squeegee movable and in a wiping action makes contact with the screen so as to press a paste through openings of the screen in a predetermined pattern onto an adjacent substrate. The squeegee comprises a cylindrically shaped object of a predetermined length having a surface covering made of a resiliently deformable material. Further, the squeegee has an external cross-sectional geometric pattern such that a first surface is pushed against the paste in the wiping action. A lower edge of the first surface is above the surface of the screen a predetermined distance, and the first surface is at a predetermined fixed angle with the screen thereby causing a spreading action of the paste on the screen surface.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.

Abstract: Data processing system architecture in which a central processing unit (CPU) and a plurality of input/output processors (I/OP), said I/OPs being connected in parallel through a bus can have access to a common working memory, under control of a memory access control unit, through a set of tridirectional gates directly connecting memory to the CPU or to the bus without interposition of registers, drivers, receivers, except said tridirectional gates, between the internal CPU channel and the memory channel. The control unit periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, absent such requests, the CPU may activate memory cycles in synchronism with its internal cycles without preamble diagloue and access waiting time.

Abstract: A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.

Abstract: A microprogrammed control apparatus for dot matrix serial printers and related printing method which allows increased horizontal resolution of the printing matrix and therefore the printing quality consistent with the restriction that no printing element can be actuated before a previous energization of any printing element has been completed. The increase of the horizontal resolution is obtained by using a character description matrix with high resolution and logic circuits responsive to binary configurations read out from such matrix. In a preferred alternative, the increase of the horizontal resolution is obtained by using a "compressed" character description matrix containing a plurality of printing patterns, one for each of the columns where printing has to be performed (hereinafter "column to be printed") and a corresponding plurality of codes, each related to a printing pattern and representative of the distance/time interval between the column to be printed and the previous column to be printed.

Abstract: A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller.