Abstract: Electromagnetic printing group for a dot matrix printer where the armature movement towards the rest position isdamped by a counterarmature interposed between the armature and a resilient element defining the rest position so that the air cushion interposed between counterarmature and armature provides a first damping action followed by the damping caused by the ballistic impact between armature and counterarmature and finally by the resilient damping of the residual energy of the armature and counterarmature.

Abstract: The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch element for selecting words stored in the first and second stack which are to be utilized as input operand words to the execution logic in response to at least one control signal.

Abstract: A write amplifier for a computer memory unit features a first and a second output terminal. The amplifier may be controlled, in the write mode, to provide output signals, on the two output terminals, of one relative polarity or the other in accordance with an applied data signal. The amplifier may be further controlled, in the read mode, to provide substantially identical signals, called a read reference voltage level, on both output terminals.

Abstract: A circuit for detecting the failure of a step motor to respond to energization commands, which takes advantage of the time constant decrease of an energized phase which occurs due to stalling of the motor. A predetermined current level I in the energized phase is reached in a time interval TI which is shorter than a time interval TO necessary to reach the same current level when there is a response of the motor. The circuit comprises a timer having a predetermined period between TI and TO which activates a bistable circuit indicative of a failure to respond if the current level I is reached in a time shorter than the required time period.

Abstract: A sheet front loading printer comprising a printer body with a chute beneath the body and having the inner portion bent upwards in order to guide a sheet inserted therein up to the platen. The platen also doubles as a sheet feeding device. To allow the use of sheets having a dimension less than the one defined by the path of the bottom of the chute, the chute is provided with at least one elongated opening or indentation and an arrangement of the printer supports which allows the printer to rest on a working plane. This permits further advancement of the sheet by manual action performed by the operator through the opening in the bottom of the chute.

Abstract: The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Abstract: What is disclosed is apparatus making up an arithmetic logic unit and utilizing a programmable read-only memory (PROM) to perform arithmetic functions for an associated processor. The PROM is used as a look-up table for computation results. Operands used to perform a mathematical computation make up an address to the PROM which is used to read out the computation result stored therein. Also stored in the PROM as part of each computation result are information bits indicating if the computation result is a valid answer. These bits are also read out and stored in flip-flops to indicate to the processor if the computation result is valid or invalid.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is an arithmetic logic unit (ALU) that functions with the CPU. The ALU has operand inputs to which are connected switched steering circuits that permit particular operands and zero operands to be selectively applied to any or all of the ALU operand inputs. This allows easy performance of special arithmetic functions such as adding a decimal operand to itself when converting the decimal operand to a binary operand, and to subtract a decimal operand from zero when complementing decimal operands.

Abstract: Apparatus is provided for addressing a memory by word and by one of a number of nibbles within a word, with the ability to increment or decrement nibble and word addresses and thereby access adjacent nibbles and words without having to generate new nibble and word addresses. An initial word address is placed in an address counter and an initial nibble address is placed in a nibble control. The two addresses indicate a particular nibble within a particular word. Thereafter, only increment or decrement signals are provided to increment and decrement the nibble address and/or the word address. A nibble counter counts the increment and decrement nibble signals and when the last or first nibble in a word is addressed, an increment or decrement word address signal is respectively generated that changes the word address stored in the address counter.

Abstract: A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.

Abstract: Rack housing for user reconfigurable EDP system comprised of a frame frontally opened to allow the insertion of a plurality of printed wired artworks (PWA) each one in a rack position. A protection ruler fixed, with the aid of tools, to the open frame front prevents the extraction from the frame of the PWA constituting a basic EDP configuration. Substitution of optional PWAs into the system via selected rack positions is accomplished by suitable undercuttings selectively arranged on the projecting edge, and by one or more panels covering the open front and removably fixed. Each panel is easily removable without need of any tool, so that the protection ruler is positioned between frame and cover panel (or panels) and cannot be removed without the previous removal of the cover panel (or panels).

Abstract: A high definition page display system for graphics and text utilizing shaped beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or grahic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines.) Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.

Abstract: A frequency and time measurement circuit is provided with a delay means for effectively delaying the leading edge of a pulse. A register is clocked by the trailing edge of the pulse to take a snapshot of how far the leading edge of the pulse has progressed through the delay means. During a calibration phase, a reference pulse of constant length is used to take a reference reading. During a measurement phase, the measurement reading is taken on the unknown pulse whose clock frequency or time period is to be determined. By comparing the reference reading with the measurement reading, the relative clock frequency or time of the unknown pulse can be determined.

Abstract: An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared.

Abstract: A high quality printing method utilizing a matrix serial printer having a print head provided with needles arranged in a vertical column. The method comprises the steps of printing a print line in two print passes, and in advancing a platen, between the first and the second pass, by an amount equal to one and a half times the vertical pitch, center to center, between two contiguous needles.

Abstract: A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to prevent loss of information. Access to the main memory is controlled by a priority resolver that awards access to the main memory on the basis of predetermined priority levels assigned to CPU, I/O and refresh requests. The priority resolver produces an early signal that is usable to initiate a memory cycle before the final winner of the main memory is determined. The logic path of the lowest priority requester is the shortest path thus allowing the lowest priority requester to initiate a memory cycle in the shortest amount of time even though another requester may ultimately win use of the memory. The priority resolver also provides for the early resetting of access requests so that subsequent requests can be made with minimum delay.

Abstract: The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read address value to a constant thereby generating a new read address value used to read the operand data on the next cycle. A preselected constant is provided to the adder each cycle, which causes the resultant new read address value to forward or reverse read the operand data.

Abstract: The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution unit of the present invention includes a first stage element which temporarily stores input data, the input data including operation commands defining said decimal type instructions, and input operand data. A second stage element executes a first predetermined group of the decimal type instructions. A third stage element, operatively coupled to said second stage element, executes a second predetermined group of the decimal type instructions, the second predetermined group including arithmetic type instructions.

Abstract: In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM unit includes an input buffer unit and an output buffer unit, a control unit to analyze an incoming DATA and provide appropriate control signals, a reconfiguration unit for reformatting the plurality of descriptor formats into a composite format, a descriptor fetch unit for retrieving a descriptor when the signals applied to the VMSM unit contain a descriptor address, and a descriptor master copy unit which contains a copy of the descriptors stored in the addressing apparatus.

Abstract: A Reader/Sorter may have an MICR read head, an OMR read head, and two OCR read heads or a combination thereof.A Reader/Sorter Adapter receives characters read by the Reader/Sorter. The characters include data and formatting symbol characters read from a document and control characters generated by the Reader/Sorter. Certain characters may be identified as queue field identifiers (QFI) by the user via software. These are usually the formatting characters. The control characters are identified as pseudo queue field identifiers (PQFI). QFI and PQFI characters are received by a Multiple Device Controller and allow the firmware to identify the length of the data fields, the head from which the characters were received, and any special conditions associated with reading of a data field.