Abstract: A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack associated with each execution unit. Collector control causes the results of the execution of instructions to program visible registers to be stored in a master safe store register in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis.

Abstract: Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions based on past history of the execution of those instructions. The prefetch mechanism forms instruction addresses and fetches instructions in parallel with the execution of previously fetched instructions by a central execution pipeline unit of the central processor unit. As instructions are prefetched, the transfer and indirect prediction (TIP) table is checked to determine the past history of those instructions. If no transfers or indirects are found, the prefetch proceeds sequentially. If transfer or indirect instructions are found, then the prefetch uses information in the TIP table to begin fetching the target instruction(s).

Abstract: A peripheral power control sequencer incorporates a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The terminals of the input/output ports of the microcomputer are time-shared to accommodate the several input and output signals needed to accomplish the sequential powering of the peripheral controller.

Abstract: In a data processing system wherein a memory is comprised of an unknown plurality of memory blocks of a basic capacity, arranged in an unknown plurality of modules which have an unknown capacity multiple of the basic capacity, a method addresses the memory location which involves the selection of the module containing such locations by use of a directory having a plurality of addressable locations.

Abstract: A data processing system having a plurality of units includes a shareable unit which is shareable between two or more of the other units. Lock apparatus is provided in the shareable unit to allow a first unit to lock the shareable unit so that no other unit attempting to lock the shareable unit will be permitted access to the shareable unit. The lock apparatus includes means that permit two units desiring to lock the shareable unit to make simultaneously asynchronous requests to lock the shareable unit. The lock apparatus further includes means to permit the unit which has locked the shareable unit to unlock the shareable unit so that it becomes available for a subsequent lock by a unit. The lock apparatus also includes means to allow the shared unit to be accessed by other units not attempting to lock the shareable unit even when the shareable unit is locked.

Abstract: A data processing system includes a cathode ray tube (CRT) display. Apparatus associated with the CRT tests and verifies the vertical and horizontal synchronization and the logic associated with a character generator. Refresh signals, horizontal synchronization signals and data bit signals from the character generator are counted. The counts of those signals which occur within a predetermined number of occurrences of vertical synchronization signals are verified.

Abstract: The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word format is different from the input data word format, selected characters in response to a predetermined control signal are temporarily stored so that they may be inputted to the shifters on the next shift cycle in order to achieve the desired shifted character order. An alignment switch then aligns or packs the shifted data from the output of the shifters to the predetermined data format in response to a select control signal.

Abstract: A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the predetermined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, a predetermined number of clock cycles (i.e. series of operations performed on the data), and the resulting signals shifted from the serial register array and signals applies to data processing unit for display or analysis.

Abstract: A cooling apparatus for a dot matrix impact print head suitable for application in serial printers. The print head is mounted on a carriage sliding on guide bars for reciprocating movement thereon. A liquid filled container having an inlet and outlet is mounted on the carriage and is in thermal contact with the printing head. A heat dissipator also mounted on the printer has a liquid filled cavity with inlet and outlet with flexible conduits connected to the inlets and outlets so as to form a liquid circulation loop. A unidirectional fluid valve in said loop maintains liquid circulation in the loop by the reciprocating movement of the liquid container.In the preferred form of embodiment the liquid container is formed integral with the print head, the liquid in the container being in direct contact with electromagnetic cores of the print head, and the heat dissipator is formed by a guiding bar, the bar being hollow and having an inlet and outlet.

Abstract: A tool facilitates the hand insertion of wire wrap square sectioned pins from a fanning metal strip into plated through holes of a wire-wrap printed circuit board. The tool includes a solid cylindrical tip which is mounted within a handle member which includes an automatic anvil. An end portion of the tip has a portion with stepped profile which contains a round hole. The hole is slightly larger than the square section of the pin and has a predetermined depth for positioning the pin in a vertical direction during an insertion operation. The sizes of the individual steps are selected to enable the pins to be ejected completely from the band portions of the strip into the holes of the board at a predetermined depth without damaging the strip or the areas surrounding the holes.

Abstract: The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of the controller section. Test mode logic circuits included within the cache memory section enable cache memories to be tested without controller interference utilizing the same controller interface circuits.

Abstract: Disclosed is a tilt-swivel base for a CRT display terminal. The base allows the CRT terminal to be readily swiveled around a vertical axis and tilted forward or backward around a horizontal axis or positioned with a combination of both movements. The cradle of the base may be placed within a recess formed in a horizontal supporting surface and thereby confine the base within the recess. By having the recess front-to-back width approximately equal to the front-to-back width of the cradle and the side to side length greater than the side to side width of the cradle, the CRT display terminal and base can be moved from side to side within the recess while still confining it to a fixed front-to-back position. By providing the cradle with a convex front surface and a triangular back surface, the base and CRT display terminal may be swiveled up to the point that one of the two angled back edges of the cradle comes into full contact with the back edge of the recess.

Abstract: The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data string length and the starting location of temporary storage memory in which the data string is to be stored is variable. A first comparator element compares a write address pointer to a start address pointer and an adder generates a sign pointer which indicates an address of temporary storage memory of the predetermined character. A second comparator element utilizes the pointers and the resultant outputs of the first comparator and the adder to indicate the end of the data string.

Abstract: A track on a disk surface of a disk drive is formatted in sectors, each sector having an address portion and a data portion. The disk drive generates a byte clock signal which increments a counter. The counter output signals address a read only memory which generates signals to control the address comparison in the address portion and the reading or writing of data bytes in the data portion of the sector.

Abstract: An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously reading and writing, in accordance with the present invention, data may be written into the register on a first half cycle of a clock signal and read out of memory on the second half cycle of the same clock signal. If the writing and the reading of the data relate to the same address in the register array, the data may be read directly from the input circuit.

Abstract: A memory module selection and reconfiguration apparatus in a data processing system wherein a modular working memory formed by a plurality of memory modules sends to a central processing unit information related to the capacities of the constituting modules (M1, M2, M3, M4) during the system initialization. The central unit processes such information and provides memory, via a channel (30), with information representative of the capacity of the first modules (G1), of the sum of the capacities of the first and second module (G2), of the sum of the capacities of the first, second and third module (G3) and so on, up to the total capacity of the working memory. This information is stored into registers (31, 32), each one related to a possible module, of a module selection unit included inside the working memory.

Abstract: A computer aided design (CAD) system is operative to generate an output containing only the additions and deletions to an existing master artwork. The CAD output is in turn applied to photoplotter equipment which produces a "delete" artwork containing line representations of only the etch/wires to be deleted from the original master artwork and an "add" artwork containing line representations of ony the etch/wires to be added to the same original master artwork. These two artworks are photographically combined with the original master artwork in a predetermined manner to produce a new PWB artwork which incorporates the added and deleted wire changes.

Abstract: A power supply for providing a selectable predetermined regulated output voltage. A switching regulator circuit provides the conversion of an input voltage to a DC output voltage and a control circuit, which senses the output voltage, controls the conversion of the switching regulator circuit. In the present invention, an amplifier, having selectable gain values, is interposed in the feedback loop, i.e., between the output terminal of the power supply and the control circuit. Thus a predetermined portion of the output voltage is fed back to the control circuit, thereby selectively determining the output voltage without necessitating changes to the switching regulator circuit or the control circuit.

Abstract: A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data processor provides predetermined signal groups and addressing apparatus responsive to the predetermined signal groups loads and unloads register arrays in response to the predetermined signals. A predetermined signal group is entered into the serial register array, a predetermined number of clock cycles are applied, and the resulting signals shifted from the serial register array are applied to the maintenance data processor for display or analysis. By comparing the expected result for a given initial state with the actual result of an operation sequence, the accuracy of the operation of the data processing system, or any portion thereof, is thereby determined.

Abstract: In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comprising a step clock generator which generates a gated clock signal. A register element receives a step command signal, an indication from the computer system that the memory unit is to be operated in the step mode, and generates the step mode control signal in response to said step command signal. A shift register receives a strobe command signal from the computer system indicating a request for a memory cycle, and delays the strobe command signal, each stage of the shift register representing a successive step when the computer system is operated in the step mode.