Abstract: This invention pertains to a power FET control circuit which operates at higher switching frequencies for reducing the output voltage ripple. The control circuit provides two pulse control signals each shifted 180.degree. out of phase, each of such signals having a fixed frequency and a duty-cycle ratio which varies up to a maximum of 50%.

Abstract: A novel method and apparatus for latching and locking D-type electrical connectors. In one embodiment a novel "bud-stud" is utilized to replace prior art isoblocks or prior art hexagonal nuts. The bud-stud is capable of mating with either a prior art screw-type or spring-loaded latching arm to latch and lock the electrical connectors to each other and to a bulkhead.

Abstract: A high definition bit mapped page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Eah beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). The invention utilizes CRTs with shaped electron beams, a bit map for storing bits utilized for generating bit patterns which are used to control the shaped electron beams.

Abstract: A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character or graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.

Abstract: A disk drive of a mass storage subsystem includes areas on a disk surface wherein a vendor-generated defective sector log, a software-generated defective sector log and an alternate sector log are stored. A random access memory (RAM) stores a copy of the defective sector logs. During a seek operation, firmware tests the defective sector logs in RAM to generate the alternate sector log for that cylinder number. During the read or write operation, the alternate sector log is checked before processing the sector to determine if it is a defective sector. If the sector is defective, the head is positioned to another cylinder at a head and sector address read from the alternate sector log.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.The bit rate of the data stream is varied depending on the number of address locations used in the data RAM of the CRT display subsystem to store each data bit.

Abstract: An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer.

Abstract: Interrupt control apparatus in a data processing system for acknowledging on a priority basis one among several possible asynchronous interruptions (INT1, INTN), such apparatus comprising a priority network (5), a latching (7) and a validation circuit (11,12). The priority network directly receives on its input terminals the asynchronous interrupt signals and provides on its output terminals a binary code corresponding to the highest priority interrupt present on its input terminals. The interrupt code is latched in the register and is present on its output terminals. The code latched in the register is used by a validation circuit as a selection code of the related input interrupt signal. If such a signal is present, the code is validated, i.e., it is transferred to the central unit of the system. If the selected interrupt signal is not present, the code is not validated.

Abstract: In a computer system, a memory system has a memory structure and means whereby the smallest memory unit, the RAM chip, may be addressed and accessed twice during each clock cycle.

Abstract: A method is disclosed for changing the horizontal and vertical resolution of an image while the image is in digitized and compressed form, where the image is first scanned and digitized to be represented as a number of discrete picture elements (pixels) and then the digitized image data is compressed. To change the resolution of an image and thereby be able to display it in smaller or larger form, the compressed image data is first analyzed and the data for certain scan lines is replicated or eliminated to respectively increase or decrease the vertical resolution of the image by a selected vertical resolution change factor. Then the compressed image data with scan lines replicated or eliminated is further processed using a selected horizontal resolution change factor to increase or decrease the horizontal resolution by respectively increasing or decreasing the number of pixels representing each scan line. The image data may also be processed so that windowing on the image may be performed.

Abstract: An optical storage card reading system using a cylindrical lens is disclosed which provides for a large viewing cone at the surface of the optical storage card thus improving the ability to read optically recorded data despite scratches or dust on the optical storage card.

Abstract: A photograph artwork containing a one to one scale exact image of the circuit pattern to appear on a fabricated printed-wiring board is modified in a predetermined manner. This has the effect of equalizing the amount of metallic conductive circuits on a double sided printed wiring board or panel. The resulting board or panel is plated uniformly on both sides when passed through the electrodeposition cycle of a fabrication process.

Abstract: A tilt base assembly includes a top plate, a horizontal base plate and a stabilizing flap which are joined together to form a pivoting wedge-shaped structure. The top plate is attachable to the bottom or base of a cathode ray tube (CRT) display terminal unit. The base plate includes a series of stops into which a free end of the stabilizing flap can be positioned after following free under the force of gravity when the terminal unit is rotated forward.

Abstract: A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock signals to selected serial arrays, a maintenance data processor for providing predetermined signal groups, and addressing apparatus responsive to the predetermined signal groups for loading and unloading register arrays in response to the predetermined signals. The disclosed apparatus permits a predetermined signal group to be entered into the serial register array, a predetermined number of clock cycles (i.e. series of operations performed on the data), and the resulting signals shifted from the serial register array and signals applies to data processing unit for display of analysis.

Abstract: The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be generated for completing the execution of the instruction. The apparatus includes a memory element, which has a plurality of locations, each of the plurality of locations corresponding to a respective location of a memory device where the operand data string is stored. The memory element stores information which indicates when the corresponding location is the last word of the operand data string. A read address register which contains the read address value of the memory device includes an input strobe terminal which receives an enable signal based on the information stored in the memory element, thereby enabling or inhibiting the updating of the read address value in the read address register.

Abstract: A probe support for a test fixture of printed circuit artworks comprising a base plate defining a supporting plane for connecting pins of a plurality of probes, a corresponding plurality of connecting elements, a cover plate designed to protect the contact tips of the probes and of connecting elements when the probe support is not to be used, etc. The base plate and the cover plate may be alternatively removed for set up and use respectively; the probes and the connecting elements being restrained to and protected by either the cover plate or the base plate. In this way both assembly of the probe support and the wiring harness between the probe pins and the pins of the connecting elements is made easier. The probe support further comprises a plate provided with a plurality of holes which house and axially guide the contact tips of the probes during active test.

Abstract: A high definition page display system for graphics and text utilizing multiple beams in a CRT is disclosed. Information for the several lines which are written simultaneously is made available in parallel. The invention is described in terms of a character set and text generation, but the same principles apply to any other graphic or bit map and to storage in ROMs or loadable RAMs. Each beam of a multiple CRT tube is biased to generate a portion of a character of graphic as it scans across the tube. It takes 12 lines to scan a character with a N-beam tube, 12 over N character scans are therefore required. With the same scanning speed as with a single beam, this factor can be used to increase definition (i.e. number of lines). Also the advantage of multiple beams can be used to reduce scanning speed, if this is useful to improve brightness or spot definition, or to increase the number of dots per line.

Abstract: Processor apparatus is described for performing binary and decimal arithmetic operations. In performing decimal multiplication with the processor apparatus, to reduce the amount of processing to be done with the apparatus and thereby speed up the performance of the decimal multiplication, the leading zeroes prefixing the highest order significant digit in both a multiplier and a multiplicand are identified, counted and removed. Decimal multiplication is then performed using the stripped multiplier and multiplicand, and to the resultant partial product a number of zeroes are prefixed equal to the number of zeroes originally stripped from the multiplier and multiplicand. The result is the product of the original multiplier and multiplicand.