Patents Assigned to Hyundai Electronics Industries Co., Ltd.
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Patent number: 7426311Abstract: An object-based coding apparatus and method for image signals, wherein upon scanning shape-adaptive transform coefficients of an input image signal transformed in accordance with a shape-adaptive transform, only segments containing such shape-adaptive transform coefficients are scanned. In the scanning operation, segments containing no transform coefficient are skipped, thereby reducing the quantity of data being encoded. An apparatus for and a method of object-based decoding of image signals are also disclosed which can decode bit streams generated using the coding method, thereby reproducing image signals.Type: GrantFiled: November 19, 1998Date of Patent: September 16, 2008Assignee: Hyundai Electronics Industries Co. Ltd.Inventors: Sung Moon Chun, Jin Hak Lee, Joo Hee Moon, Gwang Hoon Park, Jae Kyoon Kim, Jae-won Chung
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Publication number: 20080217514Abstract: A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.Type: ApplicationFiled: April 16, 2008Publication date: September 11, 2008Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Do-Young Lee
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Patent number: 7233046Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.Type: GrantFiled: April 4, 2006Date of Patent: June 19, 2007Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Chang Soo Lee
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Patent number: 7193902Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.Type: GrantFiled: April 27, 2006Date of Patent: March 20, 2007Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Hee Y. Lee
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Patent number: 7122401Abstract: An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.Type: GrantFiled: October 5, 2001Date of Patent: October 17, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Chi-Jung Song
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Publication number: 20060198203Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.Type: ApplicationFiled: April 27, 2006Publication date: September 7, 2006Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Hee Lee
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Patent number: 7095087Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.Type: GrantFiled: June 16, 2004Date of Patent: August 22, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Chang Soo Lee
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Patent number: 7088772Abstract: A method and apparatus for updating motion vector memories used for prediction of motion vectors in a video compression coding/decoding method and system. For a frame composed of N macroblocks in the horizontal direction, only (2N+1) motion vector memories are used to store all motion vectors necessary to motion prediction, and only three memories per macroblock are used to update motion vectors, thereby reducing the size of a circuitry, the amount of computation and the amount of power consumed.Type: GrantFiled: February 20, 2001Date of Patent: August 8, 2006Assignee: Hyundai Electronics Industries Co., LtdInventors: Kyeong Joong Kim, Hyun Soo Kang, Jae Won Chung
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Patent number: 7078956Abstract: A charge pump circuit is disclosed which can perform high pumping by changing the condition of connection of the charge pump circuit by connecting a serial and parallel switching circuit and a level shift circuit between unit charge pumps to construct the charge pump circuit.Type: GrantFiled: December 22, 1995Date of Patent: July 18, 2006Assignee: Hyundai Electronics Industries Co, Ltd.Inventor: Joo Young Kim
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Patent number: 7071068Abstract: A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and the substrate having a rounded profile, and then forming a complex gate electrode structure in the active region. The preferred gate electrode structure comprises a gate oxide and a stacked conductor structure having a first and a second conductor, an optional hard mask layer formed on the second conductor, an oxide layer formed on the first conductor, and nitride spacers formed on the oxide layer on the sidewalls of the gate electrode. On either side of the gate electrode structure lightly doped drain (LDD) regions and source drain regions are then formed in the active region of the semiconductor substrate. The wafer is then planarized with one or more insulating films to condition the wafer for subsequent processing.Type: GrantFiled: July 13, 2004Date of Patent: July 4, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Jae Goan Jeong
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Patent number: 7072226Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.Type: GrantFiled: April 29, 2005Date of Patent: July 4, 2006Assignee: Hyundai Electronics Industries Co, Ltd.Inventor: Hee Youl Lee
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Patent number: 7070831Abstract: A member for a semiconductor package and a semiconductor package using the member, and a method for fabricating the semiconductor package are provided to simply connect chip pads provided on a semiconductor chip to external terminals. With the member for the semiconductor package and the package using the member according to the present invention, the chip pads can simply be connected with the corresponding external terminals. In addition, since the electrical paths between the chip pads and the external leads are relatively shortened, thus the electric properties are improved. Further, since the external terminal balls can be arranged regardless of the location of the chip pads, the semiconductor package can be easily designed and the size of the package can approximate the chip size and the plurality of external balls can be provided. Also, since it is possible to perform the package process with either the wafer or the individual chip, an application range can be flexibly extended.Type: GrantFiled: December 30, 2002Date of Patent: July 4, 2006Assignee: Hyundai Electronics Industries Co.,Ltd.Inventor: Joong-Ha You
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Patent number: 7057656Abstract: A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.Type: GrantFiled: February 8, 2001Date of Patent: June 6, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Do-Young Lee
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Patent number: 7053434Abstract: A ferroelectric memory device, e.g., nonvolatile, has an effective layout by eliminating a separate cell plate line. The ferroelectric memory device includes first and second split word lines formed over first and second active regions of a semiconductor substrate, and the first and second active regions are isolated from each other. Source and drain regions are formed in the first active region on both sides of the first split word line and the second active region on both sides of the second split word line. A conductive barrier layer, a first capacitor electrode and a ferroelectric layer are sequentially formed on the first and second split word lines. Two second capacitor electrodes with one connected to one of the source and drain regions of the second active region is formed over the first split word line. The other one is connected to one of the source and drain regions of the first active region and is formed over the second split word line.Type: GrantFiled: August 11, 2005Date of Patent: May 30, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Hee Bok Kang
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Patent number: 7037796Abstract: Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700˜750° C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350˜750 C., and a nitride layer is deposited on the oxide layer.Type: GrantFiled: June 20, 2000Date of Patent: May 2, 2006Assignee: Hyundai Electronic Industries Co., Ltd.Inventors: Se Aug Jang, Tae Kyun Kim
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Patent number: 7026704Abstract: A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.Type: GrantFiled: June 14, 2004Date of Patent: April 11, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Ha Zoong Kim
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Patent number: 7012001Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a plurality of transistors formed on the semiconductor substrate and conductive plugs electrically connected to the transistors, a number of bottom electrodes formed on top of the conductive plugs, composite films formed on the bottom electrodes and Al2O3 films formed on the composite films. In the device, the composite films are made of (Ta2O5)0.92 (TiO2)0.08 by using an atomic layer deposition (ALD).Type: GrantFiled: December 8, 2003Date of Patent: March 14, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Ki-Seon Park, Byoung-Kwan Ahn
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Patent number: 7013413Abstract: The present invention relates to a packet command driving type memory device, a method for compressing output data according to the present invention is characterized to write first data of a certain bit in a corresponding address of core cell regions, read the first data of a certain bit written in the address, compare the written data and the read data by dividing it to an upper certain bit and a lower certain bit, generate compressed data of 1 bit with an information about whether a fail is.Type: GrantFiled: June 27, 2000Date of Patent: March 14, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Sung Wook Kim, In Hong Kim
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Publication number: 20060033828Abstract: A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.Type: ApplicationFiled: October 13, 2005Publication date: February 16, 2006Applicant: Hyundai Electronics Industries Co., Ltd.Inventor: Do-Young Lee
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Patent number: 6987155Abstract: The present invention relates to photoresist monomers, polymers formed therefrom and photoresist compositions suitable for photolithography processes employing a DUV light source, such as KrF (249 nm) and ArF(193 nm); EUV; VUV; E-beam; ion-beam; and X-ray. Photoresist monomers of the present invention are represented by the following Chemical Formula 1: wherein, m is 1 or 2. Polymers of the present invention comprise repeating units derived from the comonomer of Chemical Formula 1, preferably together with monomers of the following Chemical Formula 2: wherein, R* is an acid-labile group, and l is 1 or 2.Type: GrantFiled: March 21, 2003Date of Patent: January 17, 2006Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Chi Hyeong Roh, Jae Chang Jung