Abstract: The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.

Abstract: A method for monitoring at least one server in a semiconductor factory automation (FA) system, includes the steps of: a) providing server state information from at least one server to a real-time database, wherein the server state information includes an availability of a central processing unit, an availability of a disk and a state of a program process related to the server; b) storing the processor state information in the real-time database; c) retrieving the server state information to monitor the server; and d) displaying the server state information retrieved. Therefore, the method monitors at least one server in a real time so that an operator can easily locate a failure of at least one-server.

Abstract: A non-volatile memory device includes a floating gate formed over a semiconductor substrate. At one end of the floating gate, there is a tapered protrusion having a horn-like or bird's beak shape. A control gate covers the floating gate except for the tapered protrusion. Sidewall spacers are formed adjacent to the floating gate and the control gate. An erasing gate is formed over the tapered protrusion of the floating gate.

Abstract: A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile ferroelectric memory device can include first and second split wordlines formed along a first direction on a substrate at prescribed intervals, a first electrode of a first ferroelectric capacitor on the second split wordline and a first electrode of a second ferroelectric capacitor on the first split wordline, first and second ferroelectric layers respectively on surfaces of the first electrodes of the first and second ferroelectric capacitors, and second electrodes of the first and second ferroelectric capacitors, respectively, on surfaces of the first and second ferroelectric layers.

Abstract: A transistor and a method for fabricating the same that involves a forming a device isolation oxide film semiconductor substrate, forming an opening in the device isolation oxide to open the substrate and define an active region, the junction between the oxide and the substrate having a rounded profile, and then forming a complex gate electrode structure in the active region. The preferred gate electrode structure comprises a gate oxide and a stacked conductor structure having a first and a second conductor, an optional hard mask layer formed on the second conductor, an oxide layer formed on the first conductor, and nitride spacers formed on the oxide layer on the sidewalls of the gate electrode. On either side of the gate electrode structure lightly doped drain (LDD) regions and source drain regions are then formed in the active region of the semiconductor substrate. The wafer is then planarized with one or more insulating films to condition the wafer for subsequent processing.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: The present invention relates to an array of flash memory cells whose unit cell includes a single transistor of MONOS/SONOS structure (Metal/poly-Silicon Oxide Nitride Oxide Semiconductor) and to data programming and erasing using the same. The array of the flash memory cells includes a plurality of flash memory cells arranged in a form of a matrix. The matrix includes a plurality of word lines arranged in one line direction and connected to gates of the flash memory cells is a row, a plurality of selection lines arranged in a direction perpendicular to the word lines and connected to the sources of the flash memory cells arranged in a column, and a plurality of bit lines arranged in a direction parallel to the selection lines and connected to the drains of the flash memory cells of the same column. To program and erase the cells, different biasing conditions are applied to the word lines, selection lines, bit lines, and the wells of the transistors.

Abstract: A chip size stack package includes two semiconductor chips arranged such that their bond pads-forming surfaces are opposed and insulating layers are applied thereto. Via-holes for exposing bond pads are formed in the insulating layers. Metal traces exposed at both sides of the insulating layers are formed on the via-holes, whereby the insulating layers are bonded to each other and the metal traces are bonded to each other. Ends of metal wires are connected to the metal traces exposed at the insulating layers, and both sides of the chips are molded by an encapsulate leaving the other ends of the metal wires exposed.

Abstract: A nonvolatile ferroelectric memory device and a method for fabricating the same are provided that increase a process margin and simplify process steps. In addition, a number of masks is reduced to save the cost and at the same time minimize or reduce a layout area. The nonvolatile ferroelectric memory device can include first and second split wordlines formed along a first direction on a substrate at prescribed intervals, a first electrode of a first ferroelectric capacitor on the second split wordline and a first electrode of a second ferroelectric capacitor on the first split wordline, first and second ferroelectric layers respectively on surfaces of the first electrodes of the first and second ferroelectric capacitors, and second electrodes of the first and second ferroelectric capacitors, respectively, on surfaces of the first and second ferroelectric layers.

Abstract: A photomask including chromium patterns divided into two groups in such a fashion that the chromium patterns in one of the two chromium pattern groups alternate, one by one, with the chromium patterns in the other chromium pattern group, the chromium patterns being formed on two quartz substrate for the two chromium pattern groups, respectively, to prepare for the photomask, two separate photomasks each having an increased space defined between adjacent chromium patterns thereof so as to avoid a severe diffraction of light passing between the adjacent chromium patterns. A method for forming micro patterns of a semiconductor device using the photomask is also disclosed.

Abstract: A multi-level EEPROM cell and a method of manufacture thereof are provided so as to improve a program characteristic of the multi-level cell. For the purpose, the multi-level flash EEPROM cell includes a floating gate formed as being electrically separated from a silicon substrate by an underlying tunnel oxide layer, a first dielectric layer formed over the top of the floating gate, a first control gate formed on the floating gate as being electrically separated from the floating gate by the first dielectric layer, a second dielectric layer formed on the sidewall and top of the first control gate, a second control gate formed on the sidewall and top of the first control gate as being electrically separated from the first control gate by the second dielectric layer, and a source and drain formed in the substrate as being self-aligned with both edges of the second control gate.

Abstract: A method for improving scheduling fairness in using a network may include detecting whether or not a collision occurs during packet transmission in the network having a plurality of nodes; and storing and monitoring signal transmit/receive states before the collision with respect to each of the plurality of nodes; if the collision is detected, reading the previous transmit/receive states with respect to a node having the collision. The previous node state that has been read is judged and newly setting an inter packet gap (IPG) for the node. After waiting for a lapse of the IPG that has been set, a backoff is effected. After waiting for a lapse of the backoff time, a signal of the node that has been collided is retransmitted, and the status of the retransmitted signal of the node is analyzed to determine if the retransmitted signal collided. If the collision is not detected with respect to the retransmitted signal of the node, the signal transmit/receive state of the node is updated.

Abstract: A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation area. The deep well area has a second conductivity type which is opposite the first conductivity type. Also, at least one well area is formed within the deep well area.

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of (1) searching for devices between which a data transmission path is set up synchronous to different clock signals among the plurality of devices, and (2) adding a plurality of delays only to between the devices having the data transmission path set up therebetween for compensating for the delay coming from a difference of clock signals, whereby solving non-uniformity of clock signals by using a small number of delays.

Abstract: The present invention provides photoresist monomers, photoresist polymers derived from the same, processes for producing such photoresist polymers, photoresist compositions comprising such polymers, and processes for producing a photoresist pattern using such photoresist compositions. In particular, photoresist monomers of the present invention comprise a moiety of Formula 4: where R1, R2, R3 and R4 are those defined herein. Photoresist polymers of the present invention have a relatively high etching resistance, and therefore are useful in a thin resist process and a bilayer photoresist process. Moreover, photoresist polymers of the present invention have a high contrast ratio between an exposed region and a non-exposed region.

Abstract: A bit stream processing apparatus is provided which stores a bit stream in a circular buffer without separately storing a header and data of the bit stream. The bit stream processing apparatus includes: a circular buffer for storing a transmitted bit stream; a first register for indicating a first read point of the bit stream stored in the circular buffer; a first backup register for backing up data stored in the first register; a second register for storing the number of bits to be read from the circular buffer; an adder for adding the data stored in the second register and data stored in a second register; a controller for determining the number of bits to be shifted in response to the output of the adder; a third register for storing data indicative of a number of bits to be ignored from the first read point; and a second backup register for backing up data stored in the third register.

Abstract: A photoresist copolymer is prepared from one or more carboxy-substituted bicycloalkene monomers, and this copolymer is used to prepare a photoresist for submicrolithography processes employing deep ultraviolet (ArF) as a light source. In addition to having high etch resistance and thermal resistance, the photoresist has good adhesiveness to the substrate and can be developed in a TMAH solution.

Abstract: The present invention relates to a chip sized integrated circuit package. A device package embodying the invention includes: an insulative substrate having a plurality of conductive first lands formed on an upper surface of the substrate and a plurality of conductive second lands formed on a lower surface of the insulating substrate; a plurality of via holes formed in the substrate adjacent the first and second lands; a conductive film formed on inner walls of the via holes and connecting corresponding ones of the first and second lands; and at least one cavity in the substrate that has an edge extending along a in centerline of a row of the via holes. A semiconductor chip having a plurality of bond pads is attached to a center portion of the upper surface of the substrate, and a plurality in of wires connect corresponding ones of the bond pads and the first lands. An insulation resin covers the integrated circuit chip, the wires, the first lands, and the upper surface of the substrate.

Abstract: A low power audio processor is disclosed which includes a bit stream processing unit for performing bit processing for an applied audio stream and for decoding the bit processed audio stream to have a format conducive to digital signal processing; a digital signal processing unit for receiving the decoded data from the bit stream processing unit to perform digital signal processing; a post processing unit for post processing audio data from the digital signal processing unit to output final audio data; and a host interface unit for interfacing with an external device to provide an audio parallel stream from the external device to the bit stream processing unit.