Abstract: A method for preventing a diffused reflection from being generated in patterning a via hole for the metal interconnection is disclosed. The disclosed method includes: forming an insulation layer on a semiconductor substrate, wherein elements for operating a semiconductor device are formed on the semiconductor substrate; forming first photoresist patterns on the insulation layer; etching the insulation layer in order to form a first via hole using the first photoresist patterns and then forming a resulting structure; coating a first anti-reflecting coating layer on the resulting structure with a low viscosity; coating a second anti-reflecting coating layer on the resulting structure with a low viscosity; forming second photoresist patterns on the second anti-reflecting coating layer; and forming a second via hole using the second photoresist patterns.

Abstract: A photoresist copolymer is prepared from one or more carboxy-substituted bicycloalkene monomers, and this copolymer is used to prepare a photoresist for submicrolithography processes employing deep ultraviolet (ArF) as a light source. In addition to having high etch resistance and thermal resistance, the photoresist has good adhesiveness to the substrate and can be developed in a TMAH solution.

Abstract: A method for processing a lot of semiconductor wafers in a semiconductor factory automation (FA) system, wherein the lot is defined as a predetermined number of semiconductor wafers, includes the steps of: a) determining whether a first process equipment operable at a first operating mode has a job file corresponding to the lot of semiconductor wafers, wherein the job file represents data required for a semiconductor process; b) if the first process equipment operable at the first operating mode has the job file, processing the lot of semiconductor wafers according to the job file in the first process equipment; c) if the first process equipment operable at the first operating mode has not the job file, providing the job file to a second process equipment operable at a second operating mode; and d) processing the lot of semiconductor wafers according to the job file in the second process equipment.

Abstract: A method for automatically controlling an exposure time in a CMOS image sensor includes the steps of a) estimating green pixel values and counting green pixels according to respective predetermined ranges, b) calculating a first total count value and a first maximum count value of green pixels having pixel values greater than a predetermined reference range and a second total count value and a second maximum count value of the green pixels having pixel values smaller than the reference ranges, c) comparing the first total count value with the second total count value, d) comparing a third total count value of the green pixels having a pixel value within the predetermined reference range with the first maximum count value if the first total count value is greater than the second total count value, and comparing the third total count value with the second maximum count value if the second total count value is greater than the first total count value, e) capturing a next image according to a current exposure tim

Abstract: A semiconductor device and fabrication method thereof restrains an amplified current between input voltage Vin and ground voltage Vss, and first and second n-wells are biased into internal voltage sources, whereby the current-voltage characteristic of the input pad becomes stabilized during an open/short checkup of a semiconductor device. The semiconductor device includes a semiconductor substrate having a plurality of device isolation regions, first and second n-wells horizontally spaced from either of the plurality of device isolation regions, a p-channel transistor formed in the second n-well, an input protection transistor horizontally spaced from the first n-well and the device isolation region, on a symmetrical portion by the first n-well to the second n-well, and a guard ring formed between the first n-well and the input protection transistor.

Abstract: The present invention provides compounds represented by formulas 1a and 1b′; and photoresist polymers derived from the same. The present inventors have found that photoresist polymers derived from compounds of formulas 1a, 1b, or mixtures thereof, having an acid labile protecting group have excellent durability, etching resistance, reproducibility, adhesiveness and resolution, and as a result are suitable for lithography processes using deep ultraviolet light sources such as KrF, ArF, VUV, EUV, electron-beam, and X-ray, which can be applied to the formation of the ultrafine pattern of 4G and 16G DRAMs as well as the DRAM below 1G: where R1, R2 and R3 are those defined herein.

Abstract: A stacked semiconductor package including: a first chip; a plurality of first leads of which one side of each of the first leads is attached to the first chip by an insulating adhesive member and electrically connected to the first chip; a first molding compound for sealing the first chip and the first leads, including holes for exposing a predetermined portion of each of the plurality of the first leads, and the first molding compound does not cover a side of the first leads opposite the holes; a first conductive portion formed within the holes included in the first molding compound; an external terminal electrically connected to the first conductive portion; a second chip; a plurality of second leads attached on the second chip by the insulating adhesive member, and being electrically connected to the second chip; a second molding compound for sealing the second chip and the second leads, and exposing a predetermined portion of the second leads; a plurality of conductive connection units for electrically co

Abstract: A carrier frequency recovery apparatus for simultaneously reducing a frequency offset and a phase error includes: a phase detector for estimating phase error of an I-channel and Q-channel signals having a frequency offset; a select signal generator for receiving the phase error and generating a select signal; a first loop filter for attenuating the phase error by a predetermined range; a second loop filter for attenuating the phase error in a range narrower than the first loop filter; an addition unit for adding the output value of the first loop filter to an output value of the second loop filter; a multiplexer for selectively outputting an output value of the first loop filter or an output value of the addition unit in response to the select signal; and a voltage-controlled oscillator block for storing and outputting cosine and sine signals corresponding to an output value of the multiplexer.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: A thin film transistor and a fabrication method therefor, which thin transistor includes: a stepped substrate provided with a sidewall between upper portion and lower portions thereof; an active layer formed on the substrate, a gate insulation film on the active layer; a gate electrode formed on the gate insulation film corresponding to an upper part of the sidewall of the substrate; an insulation film formed on a part of the gate insulation film between the gate electrode and the lower portion of the substrate; and impurity regions formed in the active layer corresponding, to the upper and lower portions of the substrate. The impurity regions are formed by a self-aligned process using an additional mask, which controls the length of channel and offset regions in accordance with the thicknesses of the gate electrode and insulation film, respectively, for thus obtaining a more stabilized offset current and accordingly improving the reliability and reproducibility of the semiconductor device.

Abstract: The present invention discloses a method for forming a bit line of a semiconductor device which can easily perform a contact process of the semiconductor device, by forming parallel rows of I-shaped active regions, a plug poly and a ladder-type bit line. The spacing between adjacent active regions is maintained at the minimum line width. Two word lines of minimum line width and separated by the minimum line width are formed on the active region. The word lines are perpendicular to the active regions. A plug poly is formed on the active region between the word lines. A bit line contact plug is formed over the plug poly and a device isolation region. A bit line of minimum line width contacts the bit line contact plug and aligned generally parallel to the word lines is formed in a ladder-type configuration. That is, one side the lower portion of the contact plug contacts the plug poly, and the upper portion of the other side of the contact plug contacts the bit line.

Abstract: Disclosed are a capacitor for semiconductor devices capable of increasing storage capacitance and preventing leakage current, and method of manufacturing the same. The capacitor for semiconductor memory devices according to the present invention includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper portion of the dielectric layer, wherein the dielectric layer is a crystalline TaxOyNz layer, and the total of x, y, and z in the crystalline TaxOyNz layer is 1, and y is 0.3 to 0.5, and z is 0.1 to 0.3.

Abstract: A MOS transistor and a method for fabricating the MOS transistor which includes the forming a gate electrode containing an HLD film; etching the HLD film; etching a pad oxide film formed at a lower portion of the HLD film at a predetermined thickness; removing the nitride side wall spacer of an opening in the gate electrode; forming a LDD region by implanting impurity ions into the semiconductor substrate at both sides of the gate electrode; forming a side wall spacer at both sides of the gate electrode; and forming a source/drain by implanting impurity ions into the semiconductor substrate.

Abstract: Disclosed are a capacitor for a semiconductor device capable of increasing storage capacitance and preventing leakage current, and a method of manufacturing the same. According to the present invention, a lower electrode is formed on a semiconductor substrate. A surface of the lower electrode is surface-treated to prevent generation of a natural oxide layer. A TaON layer as a dielectric layer is deposited on the lower electrode. Impurities of the TaON layer are crystallized and out-diffused. And an upper electrode is deposited on the TaON layer. Herein, the TaON layer is formed by a chemical vapor reaction of Ta obtained from O2 gas and NH3 gas in an LPCVD chamber to which O2 gas and NH3 gas are supplied at a pressure of 0.1˜10 Torr at a temperature of 300˜600° C., respectively.

Abstract: A low power audio processor is disclosed which includes: a bit stream processing unit for performing bit processing for an applied audio stream and for decoding the bit processed audio stream to have a format conducive to digital signal processing; a digital signal processing unit for receiving the decoded data from the bit stream processing unit to perform digital signal processing; a post processing unit for post processing audio data from the digital signal processing unit to output final audio data; and a host interface unit for interfacing with an external device to provide an audio parallel stream from the external device to the bit stream processing unit.

Abstract: A power saving circuit for a liquid crystal panel (LCD) and a plasma display panel (PDP) recovers an energy charged in a panel capacitor through one path of a drive IC driving a scan electrode or data electrode for the PDP, and recovers the energy charged in the panel capacitor through one path of a column drive IC or row drive IC for the LCD panel. The energy recovery path can be a parasitic diode or protective diode of the drive IC. The power saving circuit can operate in an addressing period.

Abstract: A method for dynamically allocating a traffic channel element at an extended coverage of a base transceiver station which is divided by a cell site modem (CSM) ASIC in a mobile communication station is disclosed. In case that the call coverage is divided into a normal and an extended regions, the traffic channel element is not set to a pair of the normal and the extended channel elements. Instead, the channel allocation is dynamically allocated according to a channel type which is necessary on a call set up at each of the regions. The method reduces an unnecessary channel allocation and an occupation time of the channel elements, thereby enabling the capacity of the system to be increased.

Abstract: A semiconductor device isolation structure and a fabricating method therefor are disclosed. The isolation structure includes a trench which is formed on an isolating region to define an active region. First, second, and third insulating layers are deposited in the trench. The second insulating layer has an etch selection ratio different from those of the first and third insulating layers. The edge portions of the third insulating layer which contact the side walls of the trench characteristically do not show any collapse. Therefore, when supplying a subthreshold voltage, a hump phenomenon does not occur. As a result, leakage current is kept from increasing, and the device refresh characteristic can be kept from deteriorating. Further, the third insulating layer covers the top edge portions of the trench. Therefore, the gate insulating layer (which is formed later) has a sufficient thickness. Therefore, yield voltage characteristics can be kept from deteriorating.

Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.

Abstract: A mask set for measuring an overlapping error according to the invention comprises a first mask consisted of a mask substrate on which a plurality of unit patterns are formed. The plurality of unit patterns are arranged in radial shape round a given center. The mask set of the present invention further comprises a second mask consisted of a mask substrate on which a plurality of unit patterns are formed. The plurality of unit patterns of the second mask are arranged in same shape as the plurality of unit patterns of the first mask, whereby when the first and second masks are overlapped to each other, the unit pattern of the first mark and the neighboring unit pattern of the second mask maintains a certain angle.