Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract: A system, method and program product for processing a multiplicity of data update requests made by a customer. All of the data update requests are grouped into a plurality of blocks for execution by a data processor. The data update requests within each of the blocks and from one of the blocks to a next one of the blocks are arranged in an order that the data update requests need to be executed to yield a proper data result. Each of the blocks have approximately a same capacity for the data update requests. The capacity corresponds to a number of the data update requests which the data processor can efficiently process in order before processing the data update requests in the next one of the blocks. Then, the data processor processes the data update requests within the one block in the order. Then, the data processor processes the data update requests within the next block in the order. The order is an order in which the data update requests were made.

Abstract: A customizable cache discard policy is provided which reduces adverse consequences of conventional discard policies. In a data processing system, a cache controller invokes a cache data discard policy as the cache approaches its capacity. Using one possible policy, data having the shortest retrieval (fetch) time is discarded before data having longer retrieval times. In an alternative policy, data may be discarded based upon its source. Weightings may be applied based upon the distance from each source to the cache, may be based upon priorities assigned to each source, or may be based upon the type of each source.

Abstract: A method of optimizing mail sorting on a envelope sorting machine by eliminating the necessity to pass some of the documents through the machine twice is provided in which a postal code table is created having an order for each of a plurality of postal code ranges. An unsorted document print stream is received and a document parameter table created to store boundaries of each of a plurality of documents and a location of a postal code in each document. An index table is constructed incorporating information from the postal code table indicating the location and order of each document in the unsorted document print stream. The index table is reordered according to the order of each document and a sorted document print stream is generated, whereby the documents are arranged in order of their respective priorities. The documents are then printed from the sorted document print stream, separated into groups in accordance with their respective priorities and sorted in order of each group's respective order.

Abstract: A method, system and computer program product comprising: locating an import target statement in a service document; locating a generic object associated with the service document; locating import target references; loading, when a unique import target reference is located, the located target object into an address in the repository; and resolving the source document target reference to point at this address.

Abstract: A longitudinal position (LPOS) word L(n) is encoded with error correction capability. The LPOS word includes a plurality of LPOS symbols L0(n) through Lk(n) calculated as L ? ( n ) = ? i = 0 5 ? L i ? ( n ) ? 14 i and representing a longitudinal position of a magnetic tape relative to a tape head in a tape storage system. A word type is determined in response to at least one of the plurality of LPOS symbols and, in response to the determined word type, at least one formatted symbol F(n) is generated from the plurality of LPOS symbols L(n). At least one parity symbol P(n) is generated from the formatted symbol F(n). The formatted and parity symbols are communicated to a servo channel of the tape storage system to be recorded onto a servo track of the magnetic tape. Adding redundancy to LPOS words provides the capability of correcting multiple bit errors without increasing the LPOS word length.

Abstract: Methods, data structures and systems provide organize a table of contents for a volume (VTOC) stored in a storage system. The volume is divided into a plurality of ranges of tracks, including a first track range. For each track range, an associated sub-VTOC is created containing information about the contents of the track range. A master VTOC is also created containing a plurality of pointers, each pointer pointing to one of the plurality of sub-VTOCs. A first data set stored on one or more tracks within the first track range is updated and the sub-VTOC associated with the first track range is locked, whereby access to other sub-VTOCs is unaffected. The sub-VTOC associated with the first track range may then be accessed, updated and unlocked. Thus, updating data sets stored within different track ranges on the volume may proceed at the same time.

Abstract: The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si.

Abstract: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

Abstract: A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method.

Abstract: Method, apparatus and computer program product adjust gain in a read channel of a magnetic media data storage device. A digital signal sample having a data-dependent noise component is received. A gain value, stored in a location in a gain table, is selected in a data-dependent manner. The gain of the signal sample is adjusted in response to the selected gain value. A bit pattern is detected from the gain-adjusted signal sample and a data output signal is output based upon the detected bit pattern.

Abstract: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator simulator thus emulates the full system IC model. Of all possible fault injection points in the model, the test manager IHS selects a subset of those injection points for fault injection via a statistical sampling method in one embodiment. In response to commands from the test manager IHS, the simulator serially injects faults into the selected fault injection points. The test manager IHS stores results for respective fault injections at the selected injection points. If a machine checkstop or silent data corruption error occurs as a result of an injected fault, the DUT IC model may return to a stored checkpoint and resume operation from the stored checkpoint.

Abstract: An information handling system employs a processor that includes a thread priority controller. An issue unit in the processor sends branch issue information to the thread priority controller when a branch instruction of an instruction thread issues. In one embodiment, if the branch issue information indicates low confidence in a branch prediction for the branch instruction, the thread priority controller speculatively increases or boosts the priority of the instruction thread containing this low confidence branch instruction. In the manner, should a branch redirect actually occur due to a mispredict, a fetcher is ready to access a redirect address in a memory array sooner than would otherwise be possible.

Abstract: An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction.

Abstract: A system, apparatus, and method dynamically manages logical path resources by adding, removing, and establishing logic paths based on specified priority schemes associated with the logical path resources. Information associated with the logical path resources is updated in a logical path resource table.

Abstract: An apparatus, system, and method are disclosed for injecting noise onto a link of a network. The apparatus, system, and method include, providing a noise injector card, connecting the noise injector card to the link, receiving a control signal to activate the noise injector card, switching a switch of the noise injector card, and injecting noise onto the link.

Abstract: When a VTOC and a VVDS are established for information used to access data sets of a volume, unused space remains in both structures. The data sets, VTOC and VVDS are stored on a recordable medium. For VSAM data sets, other, vital information about the data set is also stored in the VTOC; for non-VSAM data sets, vital information about the data set is also stored in the VVDS. If the VOTC entry of a non-VSAM data set becomes corrupted, the vital information in the VVDS may be used to access the stored data set. Similarly, If the VVDS entry of a VSAM data set becomes corrupted, the vital information in the VTOC may be used to access the stored data set.

Abstract: An antireflective coating that contains at least two polymer components and comprises chromophore moieties and transparent moieties is provided. The antireflective coating is useful for providing a single-layer composite graded antireflective coating formed beneath a photoresist layer.

Abstract: A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples.

Abstract: A method, system, and computer program product are provided for utilizing target of opportunity to perform at least one special operation while a key session is opened with a key manager for another purpose. The method of recognizing a target of opportunity includes receiving a command to be performed on a removable storage medium and determining if the command requires interaction with the encryption key manager. If it is determined that the command requires interaction with the key manager the command is held off. A request is sent to the encryption key manager. A target of opportunity is recognized by determining if at least one special operation may be performed. If it is determined that at least one special operation may be performed then the at least one special operation and the request are performed.