Abstract: A method is provided for utilizing target of opportunity to perform at least one special operation while a removable storage medium is mounted within a data storage drive for another purpose. A target of opportunity is recognized by determining if at least one special operation may be performed by the data storage drive. If it is determined that at least one special operation may be performed then a first notification that the data storage drive is to remain in a not ready state is sent in response. At least one special operation is performed, and in response to the at least one special operation being performed, a second notification is sent that the removable storage medium is in a ready state or an error state.

Abstract: An information handling system includes a processor with an array power management controller. The array power management controller gates off a memory array, such as a cache, to conserve power whenever a group of instructions in a branch instruction queue together as a group exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment of the information handling system, the array power management controller speculatively inhibits the gating off of the memory array when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. In this manner, the array power management controller again allows access to the memory array in the event a branch redirect is likely.

Abstract: A system and computer program product are provided for utilizing target of opportunity to perform at least one special operation while a removable storage medium is mounted within a data storage drive for another purpose. The system for recognizing a target of opportunity comprises a tape drive. The tape drive receives a command to mount a tape cartridge in the tape drive, and in response the tape drive mounts the tape cartridge in the tape drive. The tape drive determines if at least one special operation may be performed. If it is determined that at least one special operation may be performed, the tape drive recognizes that a target of opportunity exists. In response to determining that at least one special operation may be performed, the tape drive sends a first notification that the tape drive is to remain in a not ready state.

Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

Abstract: A method, system and processing device for retiring data entries held within a store queue (STQ). The STQ of a processor cache is modified to receive and process several types of data entries including: non-synchronized (non-sync), thread of execution synchronized (thread-sync), and all thread of execution synchronized (all-thread-sync). The task of storing data entries, from the STQ out to memory or an input/output device, is modified to increase the effectiveness of the cache. The modified STQ allows non-sync, thread-sync, and all-thread-sync instructions to coexist in the STQ regardless of the thread of execution. Stored data entries, or stores are deterministically selected for retirement, according to the data entry type.

Abstract: A method, system and process for retiring data entries held within a store queue (STQ). The STQ of a processor cache is modified to receive and process multiple synchronized groups (sync-groups). Sync groups comprise thread of execution synchronized (thread-sync) entries, all thread of execution synchronized (all-thread-sync) entries, and regular store entries (non-thread-sync and non-all-thread-sync). The task of storing data entries, from the STQ out to memory or an input/output device, is modified to increase the effectiveness of the cache. Sync-groups are created for each thread and tracked within the STQ via a synchronized identification (SID). An entry is eligible for retirement when the entry is within a currently retiring sync-group as identified by the SID.

Abstract: A method, system, and computer program product for determining a level of cleanliness of a multi-touch screen display, characterizing objects that make contact with the screen, and initiating a specific maintenance action on the screen, based on screen cleanliness and the object(s) characterization(s). A screen diagnostic and maintenance (SDM) utility initiates a number of procedures to determine the type of object(s) and a set of characteristics of object(s) that make contact with the touch screen. Based on the results of the procedures, the SDM utility characterizes/identifies the object(s). In addition, the SDM utility initiates maintenance screen check(s) based on information stored in maintenance configuration file(s). Based on the results of the maintenance check(s), configuration file(s) data and type and characterization of the object(s) that have made contact with the screen, the SDM utility determines the type of maintenance that is performed and the timing/schedule of the maintenance action(s).

Abstract: In an automated library, data cartridges, such as magnetic tape cartridges, are stored in storage cells and accessed by data storage drives. An accessor with a gripper transports cartridges between storage cells and storage drives. Cartridges are prioritized according to their relative importance. A processor manages the placement of the cartridges in cells by having higher priority cartridges stored closer to the front of multi-cartridge cells than cartridges with a lower priority. Cartridges with a higher priority may also be stored closer to a storage drive than cartridges with a lower priority. A pusher may be used to push cartridges towards the front of multi-cartridge cells with an empty position to enable the gripper to reach the front cartridge.

Abstract: An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold.

Abstract: The present invention provides a novel method for determining the mechanical properties of the surfaces of materials including thin films. Generally, the method is comprised of laterally scanning the surface of the film with an array of cantilever tips varying temperature, load and time to obtain a measurement of mechanical properties, such as hardness and glass transition temperature. The method can be used to obtain mechanical properties of films that would otherwise be unobtainable using standard methods.

Abstract: An information handling system includes a processor integrated circuit including multiple processors with respective processor cache memories. Enhanced cache coherency protocols achieve cache memory integrity in a multi-processor environment. A processor bus controller manages cache coherency bus interfaces to master devices and slave devices. In one embodiment, a master I/O device controller and a slave I/O device controller couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller. In one embodiment, the processor bus controller blocks partial responses that it receives from all devices except the slave I/O device from being included in a combined response that the processor bus controller sends over the cache coherency buses.

Abstract: A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store.

Abstract: A method of transferring nanoparticles to a surface is provided. The method includes rotating a perimeter surface through a colloidal solution such that nanoparticles are captured by binding sites, removing liquid from the captured nanoparticles and rotating a take-up roll such that the captured nanoparticles contact a carrier surface. Moreover, the method includes removing the captured nanoparticles from the perimeter surface and transferring the nanoparticles to the carrier surface with a carrier adhesive material, rotating the carrier surface such that the transferred nanoparticles contact a target substrate, and removing the transferred nanoparticles from the carrier surface and transferring the transferred nanoparticles to the target substrate with a target substrate material.

Abstract: An integrated circuit (IC) floorplan system includes an integration design system that executes IC floorplan software on a semiconductor die IC model. The IC floorplan software includes a timing tool database of the IC model. IC integrators utilize the IC floorplan software to evaluate logic block moves within the IC model. The IC floorplan software analyzes wire interconnect signal propagation time delays that result from prospective logic block moves with the IC model. The IC floorplan software reports back in real time whether or not a prospective move of a logic block from one location to another in the IC model will cause a timing failure due to a wire interconnect time delay exceeding a predetermined timing parameter.

Abstract: A processor includes a processor core with a core interface unit that includes an age queue and a request queue. The core interface unit receives load requests from the processor core. The request queue stores the requests in respective slots of the request queue. The age queue stores ID tags in respective age queue slots. Each ID tag in the age queue corresponds to a respective address of a load instruction in the request queue. In one embodiment, ID tags propagate through the age queue at a fixed rate of two at a time from a tail of the age queue to a head of the age queue. Arbitration control circuitry generates an enable bit vector that identifies the oldest ID tag in the age queue corresponding to the oldest load request in the request queue. The arbitration circuitry selects the identified oldest instruction in the request queue as the next to dispatch. In one embodiment, the core interface unit exhibits an input frequency that is a multiple of an internal operating frequency of the core interface unit.

Abstract: A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment.

Abstract: An electronic calendar scheduling system is disclosed in which a participant schedules an event in a particular timeslot. In one embodiment, the participant may associate a timeslot importance level with the particular timeslot. When a requester later sends the participant a request to schedule another event during the already scheduled particular timeslot, the system informs the requester that the particular timeslot is either available or unavailable depending on the importance of the requester in a predetermined organization hierarchy. In one embodiment, if the requester importance level is greater than the timeslot importance level, then the system informs the requester that the already scheduled timeslot is available. Otherwise, the system informs the requester that the already scheduled timeslot is unavailable.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: Methods are provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is, changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fibre Channel over Ethernet” communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.