Abstract: Method, system and computer program product are provided for detecting and correcting dropped writes in a storage system. Data and a checksum are written to a storage device, such as a RAID array. The state of the data is classified as being in a “new data, unconfirmed” state. The state of written data is periodically checked, such as with a timer. If the data is in the “new data, unconfirmed” state, it is checked for a dropped write. If a dropped write has occurred, the state of the data is changed to a “single dropped write confirmed” state and the dropped write error is preferably corrected. If no dropped write is detected, the state is changed to a “confirmed good” state. If the data was updated through a read-modified-write prior to being checked for a dropped write event, its state is changed to an “unquantifiable” state.

Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fibre Channel over Ethernet” communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.

Abstract: A network system supports multiple network communication protocols. In one embodiment, network device driver software provides a “Fibre Channel over Ethernet” communication capability and methodology. Device driver software manages a Fibre Channel to Ethernet and Ethernet to Fibre Channel address translation in real time for data packet communications in the network system. Different embodiments of the disclosed network system include multiple name servers and network device driver software that together provide multiple adapter name discovery methodologies. In one embodiment, the adapter name discovery methodologies include port name discovery and adapter attributes discovery.

Abstract: An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure.

Abstract: A logical partition (LPAR) is managed in a data processing system by performing an initial program load (IPL), commencing execution of an application on the LPAR and selecting from a plurality of unsolicited events of which the application is to receive notice. A command is transmitted to a storage controller indicating the identity of the selected unsolicited events, wherein the storage controller will store the information in a data structure. Upon the later occurrence of an unsolicited event, the storage controller will transmit to the LPAR only notices of the selected unsolicited events.

Abstract: Deleting a data volume from a storage system and freeing its storage space to make it available to be allocated to a new volume is accomplished by only zeroing associated metadata for the tracks contained in the freed storage space which is then reused in a new volume allocation and an attempt is made by the new volume to read a first record R0 of a track. A determination is made as to whether a first user record R1 of the volume is stale If the first record R0 is stale. If record R1 is stale, the metadata or track format description (TFD) is modified whereby the entire track is indicated as being uninitialized and the first record R0 is uninitialized. If record R1 is not stale, the first record R0 is regenerated and the TFD is modified whereby the entire track is indicated as being initialized.

Abstract: A logical partition (LPAR) is managed in a data processing system by performing an initial program load (IPL), commencing execution of an application on the LPAR and selecting from a plurality of unsolicited events of which the application is to receive notice. A command is transmitted to a storage controller indicating the identity of the selected unsolicited events, wherein the storage controller will store the information in a data structure. Upon the later occurrence of an unsolicited event, the storage controller will transmit to the LPAR only notices of the selected unsolicited events.

Abstract: Deleting a data volume from a storage system and freeing its storage space to make it available to be allocated to a new volume is accomplished by only zeroing associated metadata for the tracks contained in the freed storage space which is then reused in a new volume allocation and an attempt is made by the new volume to read a first record R0 of a track. A determination is made as to whether a first user record R1 of the volume is stale If the first record R0 is stale. If record R1 is stale, the metadata or track format description (TFD) is modified whereby the entire track is indicated as being uninitialized and the first record R0 is uninitialized. If record R1 is not stale, the first record R0 is regenerated and the TFD is modified whereby the entire track is indicated as being initialized.

Abstract: An initial program load (IPL) of a logical partition (LPAR) is managed by establishing a logical path to the LPAR from a storage controller. When a notice is received by the storage controller from the LPAR that the IPL has commenced, the LPAR address is stored in a data structure. After the storage controller initiates a pack change state interrupt, the stored address is compared with the addresses in a list of all LPARS to which the interrupt is directed. If the list of addresses includes the stored address, the stored address is removed from the list. Thus, the pack change state interrupt is transmitted only to the addresses in the list, leaving the LPAR to complete the IPL without interruption. After the storage controller receives a notice from the LPAR that the IPL has completed, the address of the LPAR is removed from the data structure.

Abstract: An Ajax proxy indirection technique enables a local, front-end proxy server to handle Ajax requests from an Ajax client that must be serviced by an external Ajax server in an external domain, instead of a local Ajax back-end server exposing itself to the external domain. The front-end proxy server accepts the Ajax client's request and forwards it to the local Ajax back-end server. The proxy server asks the local AJAX server for the credentials to be used in the “external” AJAX request. The local Ajax back-end server then responds to the proxy server with meta-data for the external domain request that the proxy will make to the external domain. The proxy server uses the credentials of the “external” AJAX request to make the external request to the external Ajax server in the external domain. The proxy server performs any authentication and necessary domain mapping with the external Ajax server before sending a response from the external Ajax server back to the client.

Abstract: A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed.

Abstract: Apparatus and computer program products are provided to monitor and report performance data of a device such as a data storage drive. A plurality of quantitative values are obtained from feedback and measurement mechanisms in a data storage device of a first model during operation of the storage device. The plurality of quantitative values are normalized. Then, one or more qualitative values are generated from one or more normalized quantitative values and evaluated against corresponding baseline performance values established for the first model.

Abstract: One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instructions. A detector determines if an instruction is a high latency instruction or a low latency instruction. If the detector also finds that a particular low latency instruction is dependent on, and destructive of, a corresponding high latency instruction, then the secondary execution stage dynamically fuses the execution of the low latency instruction together with the execution of the high latency instruction. Otherwise, the primary execution stage handles the execution of the low latency instruction.

Abstract: An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m?n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.

Abstract: A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data.

Abstract: A method of generating a fingerprint of a bit sequence includes determining a relative occurrence frequency of each bit combination of a set of bit combinations in the bit sequence, wherein the set of bit combinations comprises all possible non-redundant sub-sequences of bits having at least one bit and at most a preset maximal number of bits. The method further includes determining for each bit combination of the set of bit combinations a difference value between the relative occurrence frequency of the bit combination and a random occurrence frequency, the random occurrence frequency relating to the expected random occurrence of the bit combination in the bit sequence. Moreover, the method includes allocating a set of bins, each bin of the set of bins being associated with a predetermined interval of difference values, each bin further relating to a bin value.

Abstract: The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.

Abstract: A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

Abstract: A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction.

Abstract: A calendar system includes a calendar requester client and a calendar owner client that couple to a calendar server via one or more networks therebetween. In one embodiment, when the calendar server denies a particular calendar requester access to the calendar owner's calendar, the calendar server transmits a denial notice to the calendar owner and allows the calendar owner to dynamically add the particular calendar requester to a list of approved requesters on the calendar server.