Abstract: A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Ones of the logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.

Abstract: Proximity of a mobile phone to a preferred phone is detected by radio frequency or Bluetooth equipped device, triggering automatic forwarding of calls for the mobile phone to the preferred telephone number. Automatic forwarding without user intervention can facilitate use of hands-free devices in vehicles and allow receipt of phone calls to mobile phone on regular lines in a home or office situation.

Abstract: The present invention provides a method, apparatus, and computer implemented instructions for mitigating the mobile phone nuisance factor. The present invention causes a mobile phone to activate an “In-Public-Use” profile when in a public establishment, which has a policy for mobile phone usage. A transmitter in the public establishment broadcasts an external control signal that contains an encoded command. The circuitry, or processor instructions, in a mobile phone decodes the command and activates the profile with the identified settings from the command. When the profile is activated, an icon is displayed indicating that the profile is active. Additionally, the “In-Public-Use” profile is deactivated when the mobile phone leaves the range of the signal and the previous settings of the mobile phone are enabled.

Abstract: A method and apparatus for detecting and correcting inaccuracies in curve-fitted models are provided. With the apparatus and method, humps and dips in a curve fit of actual simulation and/or empirical data are identified. After having identified the humps and dips, an analysis is performed on the humps and dips to determine if they are large enough to warrant correction. Such a determination, in a preferred embodiment, involves taking an absolute value of a difference between a value at an edge point of the hump or dip and a value at the maximum or minimum point on the hump or dip, and comparing the absolute value of the difference to the value at the edge point. If the comparison indicates that the absolute value of the difference is greater than the value at the edge point by a threshold amount, then the hump or dip is determined to be large enough to require correction.

Abstract: A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacent bitlines. A method is also presented for fabricating the flash memory array having the plurality of flash memory elements, wherein each flash memory element is configured for storing two bits.

Abstract: A method for encoding a digitized speech signal so as to generate data capable of being decoded as speech. A digitized speech signal is first converted to a series of feature vectors using for example known Mel-frequency Cepstral coefficients (MFCC) techniques. At successive instances instance of time a respective pitch value of the digitized speech signal is computed, and successive acoustic vectors each containing the respective pitch value and feature vector are compressed so as to derive therefrom a bit stream. A suitable decoder reverses the operation so as to extract the features vectors and pitch values, thus allowing speech reproduction and playback. In addition, speech recognition is possible using the decompressed feature vectors, with no impairment of the recognition accuracy and no computational overhead.

Abstract: An improved process for executing a dump is provided. The iteration loops are made “smart” by allowing them to determine how big the arrays are on the fly and adjust their behavior accordingly. The process uses a function to calculate the amount of memory to allocate for the dump list based on the dump mode and array sizes. Thus, if the static arrays are modified to add or delete constants or the diagnostic code is in an abbreviated dump mode, the amount of memory to be allocated will be calculated accurately.

Abstract: A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a deep trench DRAM device. A method is also presented for fabricating the memory system on one substrate having the SRAM device, the DRAM device and the Flash memory device.

Abstract: A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction history field, a next line address field, and a data field. The prediction history field provides information about the success of past data cache address predictions. The next line address field provides information about the predicted next data cache lines to be accessed. The data field provides data to be used by the processor. When a data line in the data cache is accessed by the processor, determines the value of a prediction history field and the value of a next line address field. If the prediction history field is true, then the next line address in the next line address field is prefetched. Based on whether the next line actually utilized by the processor matches the next line address in the next line address field, the contents of the prediction history field and the next line address filed are modified.

Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

Abstract: A data processing system, method, and computer program product are disclosed for reporting a loss of a service application to a particular system administrator. The data processing system includes a logically partitioned computer system and a hardware management console. The hardware management console is a stand-alone system separate from the computer system. A service application is executable by the hardware management console for managing service of and placing service calls for the logically partitioned computer system. The logically partitioned computer system includes a service partition. A service processor included in the logically partitioned computer system monitors a presence of the service application, and reports the absence of the service application to the service partition. In response to an absence of the service application, the service partition reports the absence of the service application to a system administrator of the service partition.

Abstract: The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approximately equal to Vdd minus Vth, where Vth represents the threshold voltage of the transfer devices of the SRAM cells. This prevents the body regions of the transfer devices of each cell of the array from fully charging up, and thus the system avoids the parasitic bipolar leakage current effects attributed to devices fabricated on a partially-depleted SOI substrate. Also, during idle or sleep mode, if all the bitlines are kept at about the Vdd minus Vth voltage level, power consumption by the SRAM architecture system is decreased. This is because the leakage path via one of the transfer gates of all the SRAM cells is greatly minimized.

Abstract: A method, an apparatus, a system, a computer program product, and a computer program are disclosed for maintaining consistency of object content (252) and metadata (204) related to the object (252) in a loose transaction model, preferably using SQL Mediated Object Manipulation (SMOM), for object and meta-data updates. The related meta-data (204) and a reference to the object (252) are stored in a table of a database. The object is stored externally to the database in an object store. The reference is used to obtain a handle for directly accessing or manipulating the external object. A version number embedded in the handle is then obtained. The embedded version number is then compared with a version number of a latest committed version of the externally stored object to determine if the handle refers to a current version of the externally stored object.

Abstract: A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which also prioritizes two simultaneous access requests slated for the DRAM cell of a data array.

Abstract: An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. Internally generated column and row addresses of defective columns and rows of each micro-cell block are stored in a memory device, such as a fuse bank, during an eDRAM macro test mode in order for the information to be quickly retrieved during each cycle of eDRAM operation to provide an SRAM-like operation. A column steering circuit steers column redundant elements to replace defective column elements. Redundancy information is either supplied from a SRAM fuse data storage device or from a TAG memory device depending on whether a read or write operation, respectively, is being performed.

Abstract: A system and method for supervising persons with a mental illness, the method comprising the steps of acquiring sensor data related to the person and the person's environment; tracking the acquired sensor data; and recognizing changes in the sensor data indicating the occurrence of an event. The method further comprises the steps of acquiring access to an event database of stored event data entries, each event data entry comprising identification of one of the sensor means, identification of the entity being sensed by the sensor means, and allowable values for the sensor data and recommendations for assistance providing actions to be taken when the received sensor data is out of range from the allowable sensor data; and recognizing the occurrence of an incident in which the received sensor data is outside of the range of the stored allowable sensor data values.

Abstract: A system and method are provided for educating an individual with the skills necessary to perform a new job, as well as providing the individual with practical work experience by providing the individual with work to perform, where the work is capable of being performed by someone having the individual's skill level.

Abstract: An UOWE is created to represent a message which is put out to the coupling facility. If it is a committed message and the PUT failed for some reason, the UOWE is flagged for “retry”. These retry UOWEs will accumulate over time. The retry logic analyzes each “retry” UOWE, extracts the log token from this UOWE, uses this log token to read a specific log record from the IMS log data set and attempts to put the committed message to the central facility again.

Abstract: A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one &mgr;W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat.

Abstract: In a chem-mech polishing process for planarizing insulators such as silicon oxide and silicon nitride, a pool of slurry is utilized at a temperature between 85° F.-95° F. The slurry particulates (e.g. silica) have a hardness commensurate to the hardness of the insulator to be polished. Under these conditions, wafers can be polished at a high degree of uniformity more economically (by increasing pad lifetime), without introducing areas of locally incomplete polishing.