Abstract: A method of identifying a network condition between a pair of network devices, wherein one of the devices comprises a jitter buffer for storing packets received via a network, the method comprising: monitoring a measure of delay in receiving media packets over the network; monitoring a size of the jitter buffer; and identifying a network condition in dependence on a change in the measure of delay and a variation in the size of the jitter buffer.

Abstract: In an example method and system, image data to an image processing module. Image data is read from memory into a down-scaler, which down-scales the image data to a first resolution, which is stored in a first buffer. A region of image data which the image processing module will request is predicted, and image data corresponding to at least part of the predicted region of image data is stored in a first buffer, in a second resolution, higher than the first. When a request for image data is received, it is then determined whether image data corresponding to the requested image data is in the second buffer, and if so, then image data is provided to the image processing module from the second buffer. If not, then image data from the first buffer is up-scaled, and the up-scaled image data is provided to the image processing module.

Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.

Abstract: Methods and ray tracing units are provided for performing intersection testing for use in rendering an image of a 3-D scene. A hierarchical acceleration structure may be traversed by traversing one or more upper levels of nodes of the hierarchical acceleration structure according to a first traversal technique, the first traversal technique being a depth-first traversal technique; and traversing one or more lower levels of nodes of the hierarchical acceleration structure according to a second traversal technique, the second traversal technique not being a depth-first traversal technique. Results of traversing the hierarchical acceleration structure are used for rendering the image of the 3-D scene. The upper levels of the acceleration structure may be defined according to a spatial subdivision structure, whereas the lower levels of the acceleration structure may be defined according to a bounding volume structure.

Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.

Abstract: A method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering, the method comprising: causing an instruction for initialising rendering of safety critical graphical data at the graphics processing unit to be provided to the graphics processing unit, said instruction comprising a request for response from the graphics processing unit; initialising a timer, said timer being configured to expire after a time period; and monitoring, during said time period, for a response from the graphics processing unit; determining, by a safety controller external to the graphics processing unit, that an initialisation error has occurred if no response is received from the graphics processing unit before the timer expires.

Abstract: A method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering within a graphics processing system, the method comprising: generating configuration data for initialising rendering of safety critical graphical data at the graphics processing unit; receiving the configuration data for initialising rendering at the graphics processing unit; configuring the graphics processing unit in accordance with the configuration data for initialising rendering; determining whether the graphics processing unit is correctly configured in accordance with the configuration data; and determining, by a safety controller external to the graphics processing unit, that an initialisation error has occurred in response to determining that the graphics processing unit is not correctly configured in accordance with the configuration data.

Abstract: A graphics processing system includes a tiling unit configured to tile a first view of a scene into a plurality of tiles, a processing unit configured to identify a first subset of the tiles that are associated with regions of the scene that are viewable in a second view, and a rendering unit configured to render to a render target each of the identified tiles.

Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor.

Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew?1),bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines are each operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of a filter with a respective data value of a data window; control logic configured to cause the multiplication logic to combine a weight with a respective data value if the weight is non-zero, and otherwise not cause the multiplication logic to combine that weight with that data value; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form an output for a respective convolution operation.

Abstract: Rendering system combines point sampling and volume sampling operations to produce rendering outputs. For example, to determine color information for a surface location in a 3-D scene, one or more point sampling operations are conducted in a volume around the surface location, and one or more sampling operations of volumetric light transport data are performed farther from the surface location. A transition zone between point sampling and volume sampling can be provided, in which both point and volume sampling operations are conducted. Data obtained from point and volume sampling operations can be blended in determining color information for the surface location. For example, point samples are obtained by tracing a ray for each point sample, to identify an intersection between another surface and the ray, to be shaded, and volume samples are obtained from a nested 3-D grids of volume elements expressing light transport data at different levels of granularity.

Abstract: A method of processing image data for an image, the image data including colour data expressed in a first colour space, transforms the colour data to a luminance-normalised colour space, and performs one or more image processing operations on the transformed colour data to generate processed image data.

Abstract: A method of estimating available bandwidth for a network comprising a transmitting device and a receiving device, the method comprising: transmitting a media packet stream over the network to the receiving device, the media packets comprising media data for streaming media at the receiving device; transmitting one or more probe packets over the network so as to test the available bandwidth of the network, wherein the probe packets comprise duplicate data of the media packet stream; and determining, during transmission of the probe packets, a measure of network bandwidth availability in dependence on one or more metrics associated with receiving the media packet stream at the receiving device.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.

Abstract: Systems and methods of geometry processing, for rasterization and ray tracing processes provide for pre-processing of source geometry, such as by tessellating or other procedural modification of source geometry, to produce final geometry on which a rendering will be based. An acceleration structure (or portion thereof) for use during ray tracing is defined based on the final geometry. Only coarse-grained elements of the acceleration structure may be produced or retained, and a fine-grained structure within a particular coarse-grained element may be Produced in response to a collection of rays being ready for traversal within the coarse grained element. Final geometry can be recreated in response to demand from a rasterization engine, and from ray intersection units that require such geometry for intersection testing with primitives. Geometry at different resolutions can be generated to respond to demands from different rendering components.

Abstract: A processor unit configured to identify blocks of a frame of a video sequence to be excluded from a motion-compensated operation, the processor unit comprising: a frame processor configured to process pixel values of a first frame to characterise blocks of one or more pixels of the first frame as representing at least a portion of a graphic object; a frame-difference processor configured to determine difference values between blocks of the first frame and corresponding blocks of a second frame, and to process said difference values to characterise blocks of the first frame as representing an image component that is static between the first and second frames; a block identifier configured to identify blocks of the first frame as protected blocks in dependence on blocks characterised as: (i) representing at least a portion of a graphic object; and (ii) representing an image component that is static between the first and second frames, wherein the identified protected blocks are to be excluded from the motion co

Abstract: A user interface to a virtual camera for a 3-D rendering application provides various features. A rendering engine can continuously refine the image being displayed through the virtual camera, and the user interface can contain an element for indicating capture of the image as currently displayed, which causes saving of the currently displayed image. Autofocus (AF) and autoexposure (AE) reticles can allow selection of objects in a 3-D scene, from which an image will be rendered, for each of AE and AF. A focal distance can be determined by identifying a 3-D object visible at a pixel overlapped by the AF reticle, and a current viewpoint. The AF reticle can be hidden in response to a depth of field selector being set to infinite depth of field. The AF and AE reticles can be linked and unlinked, allowing different 3-D objects for each of AF and AE.

Abstract: Aspects relate to tracing rays in 3-D scenes that comprise objects that are defined by or with implicit geometry. In an example, a trapping element defines a portion of 3-D space in which implicit geometry exist. When a ray is found to intersect a trapping element, a trapping element procedure is executed. The trapping element procedure may comprise marching a ray through a 3-D volume and evaluating a function that defines the implicit geometry for each current 3-D position of the ray. An intersection detected with the implicit geometry may be found concurrently with intersections for the same ray with explicitly-defined geometry, and data describing these intersections may be stored with the ray and resolved.