Abstract: A method in a hardware implementation of a Convolutional Neural Network (CNN), includes receiving a first subset of data having at least a portion of weight data and at least a portion of input data for a CNN layer and performing, using at least one convolution engine, a convolution of the first subset of data to generate a first partial result; receiving a second subset of data comprising at least a portion of weight data and at least a portion of input data for the CNN layer and performing, using the at least one convolution engine, a convolution of the second subset of data to generate a second partial result; and combining the first partial result and the second partial result to generate at least a portion of convolved data for a layer of the CNN.

Abstract: A method and intersection testing module in a ray tracing system for determining whether a ray intersects a 3D axis-aligned box that represents a volume defined by a front-facing plane and a back-facing plane for each dimension. Scaled inverse ray components are determined and a scaled minimum culling distance is determined using a result of multiplying an unscaled minimum culling distance for the ray by a predetermined magnitude. Scaled intersection distances to the planes defining the box are determined using scaled inverse ray components. The largest of the determined scaled intersection distances to a front-facing plane of the box is identified. The smallest of the determined scaled intersection distances to a back-facing plane of the box is identified. It is determined that the ray intersects the box if all of three determinations are satisfied, and it is determined that the ray misses the box if one or more of the three determinations are not satisfied.

Abstract: Apparatus for binning an input value into an array of bins, each bin representing a range of input values and the bins collectively representing a histogram of input values, the apparatus comprising: an input for receiving the input value; a memory for storing the array; and a binning controller configured to: derive a plurality of bin values from the input value according to a binning distribution located about the input value, the binning distribution spanning a range of input values and each bin value having a respective input value dependent on the position of the bin value in the binning distribution; and allocate the plurality of bin values to a plurality of bins in the array, each bin value being allocated to a bin selected according to the respective input value of the bin value.

Abstract: A graphics processing unit and method for processing fragments in a graphics processing system which includes: (i) hidden surface removal logic configured to perform hidden surface removal on fragments, and (ii) processing logic configured to execute shader programs for fragments. Initial processing of fragments is performed at the hidden surface removal logic. Some of the fragments have a shader-dependent property. A shader program for a particular fragment having the shader-dependent property is split into two stages. The initial processing comprises performing a depth test on the particular fragment. In response to the particular fragment passing the depth test of the initial processing in the hidden surface removal logic, a first stage, but not a second stage, of the shader program is executed for the particular fragment at the processing logic. The first stage of the shader program has instructions for determining the property of the particular fragment.

Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.

Abstract: Methods and tiling engines for tiling primitives in a tile based graphics processing system in which a rendering space is divided into a plurality of tiles. The method includes generating a multi-level hierarchy of tile groups, each level of the multi-level hierarchy comprising one or more tile groups comprising one or more of the plurality of tiles; receiving a plurality of primitive blocks, each primitive block comprising geometry data for one or more primitives; associating each of the plurality of primitive blocks with one or more of the tile groups up to a maximum number of tile groups such that if at least one primitive of a primitive block falls, at least partially, within the bounds of a tile, the primitive block is associated with at least one tile group that includes that tile; and generating a control stream for each tile group based on the associations, wherein each control stream comprises a primitive block entry for each primitive block associated with the corresponding tile group.

Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising an input buffer configured to provide data windows to a plurality of convolution engines, each data window comprising a single input plane; and each of the plurality of convolution engines being operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of the filter with a respective data value of the data window provided by the input buffer; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form an output for a respective convolution operation.

Abstract: A method and intersection testing module are provided in a ray tracing system for determining whether a ray intersects a 3D axis-aligned box. The box represents a volume defined by a front-facing plane and a back-facing plane for each of the dimensions of the three-dimensional axis-aligned box. Scaled ray components are determined, wherein a third scaled ray component equals 1. A scaled minimum culling distance and a scaled maximum culling distance are determined. Determined cross-multiplication values are used to identify which of the front-facing planes intersects the ray furthest along the ray and identify which of the back-facing planes intersects the ray least far along the ray. It is determined whether the ray intersects the identified front-facing plane of the box at a position that is no further along the ray than the position at which the ray intersects the identified back-facing plane.

Abstract: Circuits and associated methods for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers include calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|?|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|?|B|), and the sign of each floating-point number.

Abstract: A method and apparatus are provided for tessellating patches of surfaces in a tile based three dimensional computer graphics rendering system. For each tile in an image a per tile list of primitive indices is derived for tessellated primitives which make up a patch. Hidden surface removal is then performed on the patch and any domain points which remain after hidden surface removal are derived. The primitives are then shaded for display.

Abstract: Methods and systems for identifying quantisation parameters for a Deep Neural Network (DNN). The method includes determining an output of a model of the DNN in response to training data, the model of the DNN comprising one or more quantisation blocks configured to transform a set of values input to a layer of the DNN prior to processing the set of values in accordance with the layer, the transformation of the set of values simulating quantisation of the set of values to a fixed point number format defined by one or more quantisation parameters; determining a cost metric of the DNN based on the determined output and a size of the DNN based on the quantisation parameters; back-propagating a derivative of the cost metric to one or more of the quantisation parameters to generate a gradient of the cost metric for each of the one or more quantisation parameters; and adjusting one or more of the quantisation parameters based on the gradients.

Abstract: An echo cancellation detector for controlling an acoustic echo canceller that is configured to cancel an echo of a far-end signal in a near-end signal in a telephony system, the echo cancellation detector comprising a comparison generator configured to compare the far-end signal with the near-end signal, a decision unit configured to make a determination about a first acoustic echo canceller based on that comparison and a controller configured to control an operation of a second acoustic echo canceller in dependence on the determination.

Abstract: Methods and control stream generators for generating a control stream for a tile group comprising at least two tiles, the control stream identifying primitive blocks that are relevant to rendering at least one tile in the tile group.

Abstract: A histogram-based method of selecting a fixed point number format for representing a set of values input to, or output from, a layer of a Deep Neural Network (DNN). The method comprises obtaining a histogram that represents an expected distribution of the set of values of the layer, each bin of the histogram is associated with a frequency value and a representative value in a floating point number format; quantising the representative values according to each of a plurality of potential fixed point number formats; estimating, for each of the plurality of potential fixed point number formats, the total quantisation error based on the frequency values of the histogram and a distance value for each bin that is based on the quantisation of the representative value for that bin; and selecting the fixed point number format associated with the smallest estimated total quantisation error as the optimum fixed point number format for representing the set of values of the layer.

Abstract: A method and an intersection testing module in a ray tracing system for performing intersection testing for a ray with respect to a plurality of convex polygons, each of which is defined by an ordered set of vertices, wherein at least one of the vertices is a shared vertex which is used to define at least two of the convex polygons. The vertices of the convex polygons are projected onto a pair of axes orthogonal to the ray direction. A vertex ordering scheme defines an ordering of the projected vertices which is independent of the ordering of the vertices in the ordered sets.

Abstract: A method of identifying a network condition between a pair of network devices, wherein one of the devices comprises a jitter buffer for storing packets received via a network, the method comprising: monitoring a measure of delay in receiving media packets over the network; monitoring a size of the jitter buffer; and identifying a network condition in dependence on a change in the measure of delay and a variation in the size of the jitter buffer.

Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

Abstract: A method of initialising rendering at a graphics processing unit configured to perform safety-critical rendering, the method comprising: causing an instruction for initialising rendering of safety critical graphical data at the graphics processing unit to be provided to the graphics processing unit, said instruction comprising a request for response from the graphics processing unit; initialising a timer, said timer being configured to expire after a time period; and monitoring, during said time period, for a response from the graphics processing unit; determining, by a safety controller external to the graphics processing unit, that an initialisation error has occurred if no response is received from the graphics processing unit before the timer expires.

Abstract: In an example method and system, image data to an image processing module. Image data is read from memory into a down-scaler, which down-scales the image data to a first resolution, which is stored in a first buffer. A region of image data which the image processing module will request is predicted, and image data corresponding to at least part of the predicted region of image data is stored in a first buffer, in a second resolution, higher than the first. When a request for image data is received, it is then determined whether image data corresponding to the requested image data is in the second buffer, and if so, then image data is provided to the image processing module from the second buffer. If not, then image data from the first buffer is up-scaled, and the up-scaled image data is provided to the image processing module.

Abstract: A graphics processor architecture provides for scan conversion and ray tracing approaches to visible surface determination as concurrent and separate processes. Surfaces can be identified for shading by scan conversion and ray tracing. Data produced by each can be normalized, so that instances of shaders, being executed on a unified shading computation resource, can shade surfaces originating from both ray tracing and rasterization. Such resource also may execute geometry shaders. The shaders can emit rays to be tested for intersection by the ray tracing process. Such shaders can complete, without waiting for those emitted rays to complete. Where scan conversion operates on tiles of 2-D screen pixels, the ray tracing can be tile aware, and controlled to prioritize testing of rays based on scan conversion status. Ray population can be controlled by feedback to any of scan conversion, and shading.