Patents Assigned to Imagination Technologies
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Patent number: 11527039Abstract: Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods comprise: receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.Type: GrantFiled: November 29, 2021Date of Patent: December 13, 2022Assignee: Imagination Technologies LimitedInventors: Xile Yang, Robert Brigg, John W. Howson
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Patent number: 11520958Abstract: Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals.Type: GrantFiled: December 28, 2020Date of Patent: December 6, 2022Assignee: Imagination Technologies LimitedInventor: Robert McKemey
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Patent number: 11509330Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.Type: GrantFiled: November 13, 2020Date of Patent: November 22, 2022Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 11508028Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.Type: GrantFiled: June 29, 2019Date of Patent: November 22, 2022Assignee: Imagination Technologies LimitedInventors: Rudi Bonfiglioli, Richard Broadhurst
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Patent number: 11509450Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.Type: GrantFiled: August 5, 2019Date of Patent: November 22, 2022Assignee: Imagination Technologies LimitedInventor: Paul Rowland
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Patent number: 11507436Abstract: Methods of arbitrating between requestors and a shared resource are described. The method comprises generating a vector with one bit per requestor, each initially set to one. Based on a plurality of select signals (one per decision node in a first layer of a binary decision tree, where each select signal is configured to be used by the corresponding decision node to select one of two child nodes), bits in the vector corresponding to non-selected requestors are set to zero. The method is repeated for each subsequent layer in the binary decision tree, based on the select signals for the decision nodes in those layers. The resulting vector is a one-hot vector (in which only a single bit has a value of one). Access to the shared resource is granted, for a current processing cycle, to the requestor corresponding to the bit having a value of one.Type: GrantFiled: March 20, 2021Date of Patent: November 22, 2022Assignee: Imagination Technologies LimitedInventor: Casper Van Benthem
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Patent number: 11502973Abstract: Voice data transmission with adaptive redundancy creates a voice data packet by packetizing the voice data payload and a number of redundant payloads selected from a set of previous voice data payloads. The voice data from the voice data payload is analysed to determine whether it is a critical or non-critical payload by classifying the received voice data as voiced or unvoiced. If at least a portion of the voice data is classified as unvoiced, the voice data payload is determined to be a critical payload. If it is a critical payload, then the voice data payload is added to the set of previous voice data payloads for inclusion as a redundant payload in subsequent voice data packets. The voice data packet is then forwarded for transmission over the network.Type: GrantFiled: September 12, 2014Date of Patent: November 15, 2022Assignee: Imagination Technologies LimitedInventors: Senthil Kumar Mani, Prasad Puram
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Patent number: 11500677Abstract: A method of synchronizing a group of scheduled tasks within a parallel processing unit into a known state is described. The method uses a synchronization instruction in a scheduled task which triggers, in response to decoding of the instruction, an instruction decoder to place the scheduled task into a non-active state and forward the decoded synchronization instruction to an atomic ALU for execution. When the atomic ALU executes the decoded synchronization instruction, the atomic ALU performs an operation and check on data assigned to the group ID of the scheduled task and if the check is passed, all scheduled tasks having the particular group ID are removed from the non-active state.Type: GrantFiled: November 3, 2020Date of Patent: November 15, 2022Assignee: Imagination Technologies LimitedInventors: Ollie Mower, Yoong-Chert Foo
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Patent number: 11501494Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.Type: GrantFiled: October 2, 2020Date of Patent: November 15, 2022Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney
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Patent number: 11500463Abstract: Disclosed herein are systems and methods for controlling electronic devices based on detected brain activity. For example, a system includes a wearable over-the-ear electronic device has a set of dry EEG sensors, a camera, a processor, and programming instructions. The programming instructions cause the processor to receive images from the camera, process the images to identify features corresponding to a known device, and receive brain-wave signals from the EEG sensors. The system compares the brain-wave signals to measure a level of brain activity. Upon detection of both (a) a feature corresponding to the known device and (b) a level of brain activity that deviates from a baseline by at least a threshold level, the system generates a command signal configured to cause the known device to actuate and transmits the command signal to a controller for the known device.Type: GrantFiled: November 5, 2021Date of Patent: November 15, 2022Assignee: Imagine Technologies, Inc.Inventors: Ian Davies Troisi, Justin Henry Deegan, Connor Liam McFadden, Nicholas Albert Silenzi
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Patent number: 11494622Abstract: A method for configuring hardware for implementing a Deep Neural Network (DNN) for performing an activation function, the hardware comprising, at an activation module for performing an activation function, a programmable lookup table for storing lookup data approximating the activation function over a first range of input values to the activation module, the method comprising: providing calibration data to a representation of the hardware; monitoring an input to an activation module of the representation of the hardware so as to determine a range of input values to the activation module; generating lookup data for the lookup table representing the activation function over the determined range of input values; and loading the generated lookup data into the lookup table of the hardware, thereby configuring the activation module of the hardware for performing the activation function over the determined range of input values.Type: GrantFiled: November 5, 2018Date of Patent: November 8, 2022Assignee: Imagination Technologies LimitedInventors: Yuan Li, Antonios Tsichlas, Christopher Martin
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Patent number: 11494970Abstract: A bounce light map for a scene is determined for use in rendering the scene in a graphics processing system. Initial lighting indications representing lighting within the scene are determined. For a texel position of the bounce light map, the initial lighting indications are sampled using an importance sampling technique to identify positions within the scene. Sampling rays are traced between a position in the scene corresponding to the texel position of the bounce light map and the respective identified positions with the scene. A lighting value is determined for the texel position of the bounce light map using results of the tracing of the sampling rays. By using the importance sampling method described herein, the rays which are traced are more likely to be directed towards more important regions of the scene which contribute more to the lighting of a texel.Type: GrantFiled: May 5, 2021Date of Patent: November 8, 2022Assignee: Imagination Technologies LimitedInventors: Luke T. Peterson, Justin P. DeCell, Jens Fursund
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Patent number: 11489781Abstract: A video packet stream is transmitted from a transmitting device to a receiving device over a network, by transmitting an audio packet stream to the receiving device, determining a measure of network bandwidth in dependence on one or more metrics associated with receiving the audio packet stream at the receiving device, and enabling a video packet stream in dependence on the determined measure.Type: GrantFiled: March 17, 2021Date of Patent: November 1, 2022Assignee: Imagination Technologies LimitedInventors: Senthil Kumar Mani, Bala Manikya Prasad Puram
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Patent number: 11481951Abstract: Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region.Type: GrantFiled: February 8, 2021Date of Patent: October 25, 2022Assignee: Imagination Technologies LimitedInventors: Xile Yang, Robert Brigg
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Patent number: 11481952Abstract: An application sends primitives to a graphics processing system so that an image of a 3D scene can be rendered. The primitives are placed into primitive blocks for storage and retrieval from a parameter memory. Rather than simply placing the first primitives into a primitive block until the primitive block is full and then placing further primitives into the next primitive block, multiple primitive blocks can be “open” such that a primitive block allocation module can allocate primitives to one of the open primitive blocks to thereby sort the primitives into primitive blocks according to their spatial positions. By grouping primitives together into primitive blocks in accordance with their spatial positions, the performance of a rasterization module can be improved. For example, in a tile-based rendering system this may mean that fewer primitive blocks need to be fetched by a hidden surface removal module in order to process a tile.Type: GrantFiled: September 30, 2020Date of Patent: October 25, 2022Assignee: Imagination Technologies LimitedInventors: Xile Yang, John W. Howson, Jonathan Redshaw
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Patent number: 11481954Abstract: Systems and methods for producing an acceleration structure provide for subdividing a 3-D scene into a plurality of volumetric portions, which have different sizes, each being addressable using a multipart address indicating a location and a relative size of each volumetric portion. A stream of primitives is processed by characterizing each according to one or more criteria, selecting a relative size of volumetric portions for use in bounding the primitive, and finding a set of volumetric portions of that relative size which bound the primitive. A primitive ID is stored in each location of a cache associated with each volumetric portion of the set of volumetric portions. A cache location is selected for eviction, responsive to each cache eviction decision made during the processing. An element of an acceleration structure according to the contents of the evicted cache location is generated, responsive to the evicted cache location.Type: GrantFiled: February 2, 2021Date of Patent: October 25, 2022Assignee: Imagination Technologies LimitedInventors: James A. McCombe, Aaron Dwyer, Luke T. Peterson, Neils Nesse
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Patent number: 11475193Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.Type: GrantFiled: February 4, 2021Date of Patent: October 18, 2022Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Sam Elliott
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Patent number: 11468622Abstract: A method of controlling the order in which primitives generated during tessellation are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.Type: GrantFiled: December 30, 2020Date of Patent: October 11, 2022Assignee: Imagination Technologies LimitedInventor: Peter Malcolm Lacey
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Patent number: 11468620Abstract: A graphics processing engine has a geometry shading stage having two modes of operation. In the first mode of operation, each primitive output by the geometry shading stage is independent, whereas in the second mode of operation, connectivity between input primitives is maintained by the geometry shading stage. The mode of operation of the geometry shading stage can be determined based on the value of control state data which may be generated at compile-time for a geometry shader based on analysis of that geometry shader.Type: GrantFiled: January 17, 2019Date of Patent: October 11, 2022Assignee: Imagination Technologies LimitedInventor: John W. Howson
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Patent number: 11467840Abstract: Livelock recovery circuits configured to detect livelock in a processor, and cause the processor to transition to a known safe state when livelock is detected. The livelock recovery circuits include detection logic configured to detect that the processor is in livelock when the processor has illegally repeated an instruction; and transition logic configured to cause the processor to transition to a safe state when livelock has been detected by the detection logic.Type: GrantFiled: January 15, 2020Date of Patent: October 11, 2022Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton